9 Appendix
9.1 Data image of the technology modules
XI/ON: XNE-GWBR-2ETH-MB
10/2011 MN05002008Z-EN
www.eaton.com
173
4,5
MSG_PWMx_DO_ERR
0
No error message from outputs Px / Dx.
1
One of the outputs Px (Px_DIAG) or Dx
(Dx_DIAG) of the corresponding PWMx-
channel sent an error.
STS_PWMx_GENERAL_EN 0
Function (PWMx) disabled
1
Function enabled, with a change from 0
→
1
the channel is set to the initial state
STS_PWMx_RUN
0
PWMx-signal output not active
1
PWMx-signal output active
STS_PWMx_SFKT_EN
0
Special function of Z disabled for PWMx
1
Special function of Z enabled for PWMx
STS_PWMx_LOGMSG
0
Curent status of MSG bits
1
Status of MSG bits are frozen
Communication
6
Dx
0
Digital input is LOW
1
Digital input is HIGH
STS_DBPx
0
Status of the information defined through
DBPx STS MODE.
1
STS_CONFIG _ERR
0
The present configuration is OK.
1
In REG_CONFIG_ERR an error is reported
REG_RD_ABORT
0
The reading of the register defined in
REG_RD_ADR has been accepted and
executed. The content of the register can be
found in the user data (REG_RD_DATA).
1
Reading of the register defined in
REG_RD_ADR has not been accepted. The
register content (REG_RD_DATA) is zero.
REG_WR_AKN
0
A change of register contents had been
assigned through a process output.
1
No change of register contents through a
process output. (Write access REG_WR to the
register interface is only possible, if this bit
was zero before; handshake for data transfer
to the registers).
Table 80:
Process input
data / check-
back interface of
XNE-2CNT-
2PWM
Byte Bit
Value
Meaning