9 Appendix
9.1 Data image of the technology modules
178
XI/ON: XNE-GWBR-2ETH-MB
10/2011 MN05002008Z-EN
www.eaton.com
5
REG_WR
0
Initial state
1
Triggering a write command. The register of
which the address has been defined with
REG_WR_ADR, will be written with data from
REG_WR_DATA.
6
REG_WR_ADR
0…127
Address of the register, which has to be
written with REG_WR_DATA (
→
see below).
7
REG_RD_ADR
0…127
Address of the register, which has to be read.
The user data can be found in REG_RD_DATA
in the Process input / check-back interface) if
RD_ABORT = 0.
User data
8
…
11
REG_WR_DATA, Byte 0
...
REG_WR_DATA, Byte 3
0332
32
-1 Value which, during a write operation, has to
be written to the register selected with
REG_WR_ADR (
→
see above).
12
…
15
AUX_REGx_WR_DATA,
Byte 0
...
AUX_REGx_WR_DATA,
Byte 3
0…2
32
-1 Value which, during a write operation, has to
be written to the register defined in
(ADR AUX REGx WR DATA) in the parameter-
ization.
Table 81:
Process output
data / control
interface of
XNE-2CNT-
2PWM
Byte Bit
Value
Meaning