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PCI#2 Access #1 Retry
Default: Enabled
When set to Enabled, the AGP Bus (PCI#2) access to PCI Bus (PCI#1)
is executed with the error retry feature.
AGP Master 1 WS Write
Default: Disabled
This implements a single delay when writing to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
AGP Master 1 WS Read
Default: Disabled
This implements a single delay when reading to the AGP Bus. By de-
fault, two-wait states are used by the system, allowing for greater
stability.
Memory Parity/ECC Check
Default: Disabled
Enable this item to allow BIOS to perform a parity check to the POST
memory tests. Select Enabled only if the system DRAM supports parity
checking.
Summary of Contents for P6VXM2
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