ELAN Microelectronics Corporation EM78P911A Manual Download | Manualshive

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EM78P911A

8-bit Micro-controller

__________________________________________________________________________________________________________________________________________________________________

* This specification is subject to change without notice.

~ ~

20

12/19/2005 (V2.1)

:

MOV 0X03,A

:

SWAPA A_BUFFER

;Return ACC

: RETI

VII.7 Instruction Set

Instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.

The symbol "R" represents a register designator which specifies which one of the 64 registers (including

operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the
selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'',
affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.

INSTRUCTION BINARY

HEX

MNEMONIC

OPERATION

STATUS
AFFECTE
D

0 0000 0000 0000

0000

NOP

No Operation

None

0 0000 0000 0001

0001

DAA

Decimal Adjust A

C

0 0000 0000 0010

0002

CONTW

A

→

CONT

None

0 0000 0000 0011

0003

SLEP

0

→

WDT, Stop oscillator

T,P

0 0000 0000 0100

0004

WDTC

0

→

WDT

T,P

0 0000 0000 rrrr

000r

IOW R

A

→

IOCR

None

0 0000 0001 0000

0010

ENI

Enable Interrupt

None

0 0000 0001 0001

0011

DISI

Disable Interrupt

None

0 0000 0001 0010

0012

RET

[Top of Stack]

→

PC

None

0 0000 0001 0011

0013

RETI

[Top of Stack]

→

PC

Enable Interrupt

None

0 0000 0001 0100

0014

CONTR

CONT

→

A

None

0 0000 0001 rrrr

001r

IOR R

IOCR

→

A

None

0 0000 0010 0000

0020

TBL

R2+A

→

R2 bits 9,10 do not

clear

Z,C,DC

0 0000 01rr rrrr

00rr

MOV R,A

A

→

R

None

0 0000 1000 0000

0080

CLRA

0

→

A

Z

0 0000 11rr rrrr

00rr

CLR R

0

→

R

Z

0 0001 00rr rrrr

01rr

SUB A,R

R-A

→

A

Z,C,DC

0 0001 01rr rrrr

01rr

SUB R,A

R-A

→

R

Z,C,DC

0 0001 10rr rrrr

01rr

DECA R

R-1

→

A

Z

0 0001 11rr rrrr

01rr

DEC R

R-1

→

R

Z

0 0010 00rr rrrr

02rr

OR A,R

A

∨

V

R

→

A

Z

0 0010 01rr rrrr

02rr

OR R,A

A

∨

V

R

→

R

Z

0 0010 10rr rrrr

02rr

AND A,R

A & R

→

A

Z

0 0010 11rr rrrr

02rr

AND R,A

A & R

→

R

Z

0 0011 00rr rrrr

03rr

XOR A,R

A

⊕

R

→

A

Z

0 0011 01rr rrrr

03rr

XOR R,A

A

⊕

R

→

R

Z

0 0011 10rr rrrr

03rr

ADD A,R

A + R

→

A

Z,C,DC

0 0011 11rr rrrr

03rr

ADD R,A

A + R

→

R

Z,C,DC

0 0100 00rr rrrr

04rr

MOV A,R

R

→

A

Z

0 0100 01rr rrrr

04rr

MOV R,R

R

→

R

Z

0 0100 10rr rrrr

04rr

COMA R

/R

→

A

Z

0 0100 11rr rrrr

04rr

COM R

/R

→

R

Z

0 0101 00rr rrrr

05rr

INCA R

R+1

→

A

Z

«
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20
21
22
23
...
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Summary of Contents for EM78P911A

Page 1: ...2005 12 19 EM78P911A 8 BIT MICRO CONTROLLER ELAN MICROELECTRONICS CORP No 12 Innovation 1st RD Science Based Industrial Park Hsin Chu City Taiwan TEL 03 5639977 FAX 03 5630118 SA2 Version 2 1 ...

Page 2: ...____________________________________________________________________________________________________________ This specification is subject to change without notice 1 12 19 2005 V2 1 Version history Date Version number Description Note 2005 12 19 2 1 Add DTMF detail description in page 33 ...

Page 3: ...tive signal sources and trigger edges and with overflow interrupt Programmable free running on chip watchdog timer 99 9 single instruction cycle commands Four modes internal clock 3 579MHz 1 Sleep mode CPU and 3 579MHz clock turn off 32 768KHz clock turn off 2 Idle mode CPU and 3 579MHz clock turn off 32 768KHz clock turn on 3 Green mode 3 579MHz clock turn off CPU and 32 768KHz clock turn on 4 No...

Page 4: ...M7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 VSS TEST COM8 P60 COM9 P61 COM10 P62 COM11 P63 COM12 P64 COM13 P65 COM14 P66 COM15 P67 SEG40 P54 SEG41 P55 SEG42 P56 SEG43 P57 SEG44...

Page 5: ...G8 SEG9 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 VSS TEST COM8 P60 COM9 P61 COM10 P62 COM11 P63 COM12 P64 COM13 P65 COM14 P66 COM15 P67 SEG40 P54 SEG41 P55 SEG42 P56 SEG43 P57 SEG44 P80 SEG45 P81 SEG46 P82 SEG47 P83 SEG48 P84 SEG49 P85 SEG50 P86 SEG51 P87 SEG52...

Page 6: ...iagram2 CP U CPU TIMING CONTROL TIMING CONTROL TIME R TIMER RO M ROM RA M RAM LCD DRIVER LCD DRIVER LCD IO PORT IO PORT I O FSK DTMF CALL WAITING SDT MEI RTF Xin Xout Oscillator timing control Control sleep and wake up on I O port R1 TCC WDT timer prescalar GENERAL RAM R4 Interruption control ROM Instruction register Instruction decoder R2 STACK ALU ACC R3 R5 DATA CONTROL BUS 2 5 k RAM PORT6 IOC6 ...

Page 7: ...ted pair lines for FSK RING I Should be connected with RING side of twisted pair lines for FSK CWTIP I Should be connected with TIP side of twisted pair lines for CW GAIN I OP output pin for gain adjustment RDET1 I Detect the energy on the twisted pair lines These two pins coupled to the twisted pair lines through an attenuating network RING TIME I Determine if the incoming ring is valid An RC net...

Page 8: ...n codes JMP instruction allows the direct loading of the low 10 program counter bits CALL instruction loads the low 10 bits of the PC PC 1 and then push into the stack RET RETL k RETI instruction loads the program counter with the contents at the top of stack MOV R2 A allows the loading of an address from the A register to the PC and the ninth and tenth bits are cleared to 0 ADD R2 A allows a rela...

Page 9: ...n t care Bit 5 SDT Read Only Stuttered dial tone signal detect output 0 1 SDT signal valid SDT signal invalid Bit 6 PAGE change IOCB IOCE to another page 0 1 page0 page1 Bit 7 CAS CALL WAITING Output 0 1 CW data valid No data 5 R4 RAM Select Register Bits 0 5 are used to select up to 64 registers in the indirect addressing mode Bits 6 7 determine which bank is activated among the 4 banks See the c...

Page 10: ...intain program page by user Otherwise user can use far jump FJMP or far call FCALL instructions to program user s code And the program page is maintained by EMC s complier It will change user s program by inserting instructions within program Bit4 7 PORT5 4 bit I O register 6 R6 R9 Port 6 Port 9 Four 8 bit I O registers 7 RA FSK Status Register bit 0 1 2 4 read only 7 6 5 4 3 2 1 0 IDLE 358E LPD L...

Page 11: ...tween Bit0 to Bit3 Bit4 Read Only Low battery signal 0 1 Battery voltage is low Normal Low battery detect level is set by external resisters R1 and R2 The detect level VbL 0 87V 1 R1 R2 If Vbattery is under VbL then send a 0 signal to LOW_BAT bit othwise a 1 signal to this bit Select pin P77 LBD as LBD by setting IOCE PAGE0 bit1 to 0 LBD pin is used as low battery detect input Bit5 read Write Low ...

Page 12: ...up signal is a rising or falling signal defined by CONT REGISTER bit7 RINGTIME pin Port9 Port71 Port72 and Port73 s wakeup signal is a falling edge signal 8 RB DTMF tone row and column register read write 7 6 5 4 3 2 1 0 c7 c6 c5 c4 r3 r2 r1 r0 Bit 0 Bit 3 are row frequency tone Bit 4 Bit 7 are column frequency tone Initial RB is equal to high Bit 7 0 are all 1 turn off DTMF power bit 3 0 Row freq...

Page 13: ... circuit When Call waiting circuit is powered on PLL is also enabled regardless of RA bit6 358E When Call waiting circuit is powered off PLL status is depended on RA bit6 358E setting WURING RINGTIME WUP9L PORT9 3 0 WUP9H PORT9 7 4 WDTE WDTEN 0 1 enable disable Fig 9 Wake up function and control signal 12 RF Interrupt Status Register 7 6 5 4 3 2 1 0 INT3 FSK CW C8_2 C8_1 INT2 INT1 INT0 TCIF 1 mean...

Page 14: ...by ENI RETI instructions Bit 7 INT_EDGE 0 P70 s interruption source is a rising edge signal 1 P70 s interruption source is a falling edge signal CONT register is readable and writable 3 IOC5 I O Port Control Register 7 6 5 4 3 2 1 0 IOC57 IOC56 IOC55 IOC54 MEIO RTFO RTFPWR P5S Bit0 P5S is switch register for I O port or LCD signal switching 0 1 normal I O port SEGMENT output Bit1 RTFPWR power cont...

Page 15: ...DTPW At this time setting SDTPW 1 0 power on circuit power down circuit Bit6 port8 low nibble switch 0 1 normal I O port SEGMENT output Bit7 port8 high nibble switch 0 1 normal I O port SEGMENT output 6 IOCB LCD ADDRESS PAGE0 Bit6 Bit0 LCDA6 LCDA0 The LCD display data is stored in the data RAM The relation of data area and COM SEG pin is as below COM15 COM8 COM7 COM0 40H Bit15 Bit8 00H Bit7 Bit0 S...

Page 16: ...cted disconnected the R9 will read as 0 1 when RO is set to 1 9 IOCE Bias PLL Control Register PAGE0 7 6 5 4 3 2 1 0 P9SH P9SL P6S Bias3 Bias2 Bias1 LBD P77 SC Bit 0 SC SCAN KEY signal 0 1 disable enable Once you enable this bit all of the LCD signal will have a low pulse during a common period This pulse has 30us width Please use the procedure to implement the key scan function a set port7 as inp...

Page 17: ...0VDD 0 66VDD 0 74VDD 0 82VDD 0 87VDD 0 93VDD 0 96VDD 1 00VDD 3 0V 3 3V 3 7V 4 0V 4 4V 4 7V 4 8V 5 0V Bit5 port6 switch 0 1 normal I O port COMMON output Bit6 port9 low nibble switch 0 1 normal I O port SEGMENT output Bit7 port9 high nibble switch PAGE1 7 6 5 4 3 2 1 0 OP77 OP76 C2S C1S PSC1 PSC0 CDRD 0 Bit0 unused Bit1 cooked data or raw data select bit 0 1 cooked data raw data Bit3 Bit2 counter1 ...

Page 18: ...is available for TCC or WDT determined by the status of the bit 3 PAB of the CONT register See the prescaler ratio in CONT register Fig 10 depicts the circuit diagram of TCC WDT Both TCC and prescaler will be cleared by instructions which write to TCC each time The prescaler will be cleared by the WDTC and SLEP instructions when assigned to WDT mode The prescaler will not be cleared by SLEP instru...

Page 19: ...enabled and in GREEN or NORMAL mode Note that only Power on reset or only Voltage detector in Case 1 is enabled in the system by CODE Option bit If Voltage detector is disabled Power on reset is selected in Case 1 Refer to Fig 12 Fig 12 Block diagram of Reset of controller Once the RESET occurs the following functions are performed The oscillator is running or will be started The Program Counter R...

Page 20: ...ister RF is the interrupt status register which records the interrupt request in flag bit IOCF is the interrupt mask register Global interrupt is enabled by ENI instruction and is disabled by DISI instruction When one of the interrupts when enabled generated will cause the next instruction to be fetched from address 008H Once in the interrupt service routine the source of the interrupt can be dete...

Page 21: ...1 DAA Decimal Adjust A C 0 0000 0000 0010 0002 CONTW A CONT None 0 0000 0000 0011 0003 SLEP 0 WDT Stop oscillator T P 0 0000 0000 0100 0004 WDTC 0 WDT T P 0 0000 0000 rrrr 000r IOW R A IOCR None 0 0000 0001 0000 0010 ENI Enable Interrupt None 0 0000 0001 0001 0011 DISI Disable Interrupt None 0 0000 0001 0010 0012 RET Top of Stack PC None 0 0000 0001 0011 0013 RETI Top of Stack PC Enable Interrupt ...

Page 22: ...1 00kk kkkk kkkk 1kkk CALL k PC 1 SP Page k PC None 1 01kk kkkk kkkk 1kkk JMP k Page k PC None 1 1000 kkkk kkkk 18kk MOV A k k A None 1 1001 kkkk kkkk 19kk OR A k A k A Z 1 1010 kkkk kkkk 1Akk AND A k A k A Z 1 1011 kkkk kkkk 1Bkk XOR A k A k A Z 1 1100 kkkk kkkk 1Ckk RETL k k A Top of Stack PC None 1 1101 kkkk kkkk 1Dkk SUB A k k A A Z C DC 1 1110 0000 0001 1E01 INT PC 1 SP 001H PC None 1 1110 10...

Page 23: ... without notice 22 12 19 2005 V2 1 Bits 5 7 unused VII 8 2 PAD Option POVD power on voltage detect reset can be enabled disabled by PAD Option This POVD pad is not shown on the pin assignment Internally or externally connecting this pad to GND VDD to enable disable POVD reset POVD 2 2V reset power on reset Low power detect without reset Low power detect controlled by RA 5 sleep mode current 1 No y...

Page 24: ...this signal to wake up whole chip or read RD signal from RA register A FSKPWR input is provided to activate the block regardless of the presence of a power ring signal If FSKPWR is sent low the FSK block will power down whenever it detects a valid ring signal it will power on when FSKPWR is high The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feed...

Page 25: ...l in RA throught a buffer Fig 14 ring detect circuit VII 10 DTMF Dual Tone Multi Frequency Tone Generator Built in DTMF generator can generate dialing tone signals for telephone of dialing tone type There are two kinds of DTMF tone One is the group of row frequency the other is the group of column frequency each group has 4 kinds of frequency user can get 16 kinds of DTMF frequency totally DTMF ge...

Page 26: ... turn off DTMF power bit 3 0 Row freq 1110 699 2Hz 1 2 3 A 1101 771 6Hz 4 5 6 B 1011 854Hz 7 8 9 C 0111 940 1Hz 0 D Column freq 1203Hz 1331 8Hz 1472Hz 1645 2Hz bit 7 4 1110 1101 1011 0111 VII 11 LCD Driver The CALLER ID IC can drive LCD directly and has 60 segments and 16 commons that can drive 60 16 dots totally LCD block is made up of LCD driver display RAM segment output pins common output pins...

Page 27: ...rol LCD_M duty bias 0 0 change duty Disable turn off LCD 0 1 1 16 1 4 1 8 1 4 0 1 Blanking 1 1 LCD display enable VII 11 2 LCD display area The LCD display data is stored in the data RAM The relation of data area and COM SEG pin is as below COM15 COM8 COM7 COM0 40H Bit15 Bit8 00H Bit7 Bit0 SEG0 41H 01H SEG1 7BH 3BH SEG59 7CH 3CH empty 7DH 3DH empty 7EH 3EH empty 7FH 3FH empty IOCB LCD Display RAM ...

Page 28: ...COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM15 1 8 o o o o o o o o x x 1 16 o o o o o o o o o o x open o select SEG signal The 60 segment signal pins are connected to the corresponding display RAM address 00h to 3Bh The high byte and the low byte bit7 down to bit0 are correlated to COM15 to COM0 respectively When a bit of display RAM is 1 a select signal is sent to the corresponding segment pin and when...

Page 29: ...rol Register 7 6 5 4 3 2 1 0 Bias3 Bias2 Bias1 Bit 2 4 Bias1 Bias3 Control bits used to choose LCD operation voltage The circuit can refer ti figure15 LCD operate voltage Vop VDD 5V VDD 5V 000 001 010 011 100 101 110 111 0 60VDD 0 66VDD 0 74VDD 0 82VDD 0 87VDD 0 93VDD 0 96VDD 1 00VDD 3 0V 3 3V 3 7V 4 0V 4 4V 4 7V 4 8V 5 0V Bit 5 7 unused 78810 78910 Vdd Vlcd Vop Vss Vop Vdd Vlcd R 1K R R R R V1 V2...

Page 30: ...Number Deliver feature which is offered by regional Bell Operating Companies The call waiting decoder has four blocks including pre amplifier band pass filter level detect and digital detection algorithm In a typical application after enabling CW circuit by RE BIT7 CWPWR this IC receives Tip and Ring signals from twisted pairs The signals as inputs of pre amplifier and the amplifier sends input si...

Page 31: ...timing VII 14 MEI and RTF Function Description Based on TIA EIA 777 or TIA SP 4078 protocol MEI Multiple Extension Internetworking allows Type 2 and 3 CPE to dynamically arbitrate responsibility for completing the CAS ACK handshake Also RTF Request to Flash allows Type 2 and 3 CPE to synchronize line flash signal after CAS ACK handshaking For MEI part protocol shows line voltage below 19V as line ...

Page 32: ...old Voltage RESET TCC RDET1 2 0 V VILT Input Low Threshold Voltage RESET TCC RDET1 0 8 V VIHX Clock Input High Voltage OSCI 3 5 V VILX Clock Input Low Voltage OSCI 1 5 V VHscan Key scan Input High Voltage Port6 for key scan 3 5 V VLscan Key scan Input Low Voltage Port6 for key scan 1 5 V VOH1 Output High Voltage port6 7 8 IOH 1 6mA 2 4 V port9 IOH 6 0mA 2 4 V VOL1 Output Low Voltage port6 7 8 IOL ...

Page 33: ...ll waiting Band Pass Filter AC Characteristic VDD 5V Ta 25 C CHARACTERISTIC MIN TYP MAX UNIT input sensitivity TIP and RING pins Vdd 5V Input G 1 38 dBm Minimum access frequency deviation for EM78P911A 0 5 Description Symbol Min Typ Max Unit OSC start up 32 768KHz 3 579MHz PLL Tosc 400 10 ms FSK AC Characteristic Carrier detect low Tcdl 10 14 ms Data out to Carrier det low Tdoc 10 20 ns Power up t...

Page 34: ... without notice 33 12 19 2005 V2 1 DTMF tone generator AC characteristic Vdd 5V Ta 25 2 Characteristic MIN Typ MAX Unit Tone1 Tone2 signal strength root mean square voltage Tone1 signal strength V1 rms Ps1 130 155 180 mV Tone2 signal strength V1 rms Ps1 1 259 V1 rms mV Tone twist Tone1 Tone2 twist 2 dB Tone frequency deviation Frequency deviation 1 Ps1 V1 rms and V2 rms has 2dB different It means ...

Page 35: ..._____________________________________________________________________________________________________________________________________________ This specification is subject to change without notice 34 12 19 2005 V2 1 XI Timing Diagrams ins Fig 18 AC timing ...

Page 36: ... notice 35 12 19 2005 V2 1 Fig 19 FSK Timing Diagram Fig 20 Call Waiting Timing Diagram Fig 21 Stuttered dial tone detect timing diagram PCW Power power off power on on off events Td plug in on hook in use CAS Tcasi CAS Tr normal TIP RING RING TIME RD CD DATA OSC FIRST RING 2 SECONDS 0 5 SEC 0 5 SEC SECOND RING 2 SECONDS DATA 3 579 MHz Tcdl 358E Tosc Tdoc Tpd Tsup Tcdh Trd TIP RING SDT SDT signal ...

Page 37: ...er can connect 1M ohms resistor between TIP pin and RING pin Fig 21 APPLICATION CIRCUIT 1 2 3 4 A B C D 4 3 2 1 D C B A Title Number Revision Size A Date 18 May 1999 Sheet of File C ADVSCH 78911_1 SCH Drawn By TIP RING DET1 RINGTIME AVSS VSS TEST CWTIP GAIN COMMON SEGMENT AVDD VDD EST ST GT PLLC XIN XOUT RESET LCD DISPLAY 0 22u 270K VDD 470K 33K 10K 10K 300K 100 32768 0 01u 27 0 1u 0 1u 0 1u 250V ...

Page 38: ...46 147 148 149 150 151 152 153 154 155 156 157 158 159 160 TEST SEG44 P80 SEG45 P81 SEG46 P82 SEG47 P83 SEG48 P84 SEG49 P85 SEG50 P86 SEG51 P87 SEG52 P90 SEG53 P91 SEG54 P92 SEG55 P93 SEG56 P94 SEG57 P95 SEG58 P96 SEG59 P97 VDD R32K VSS IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 INSEND IRSEL PH1OUT X2OUT HOLD POVD ENTCC MCLK SEG39 SEG38 SEG37 SEG36 LBD P77 P76 P75 P74 P73 INT3 P72 INT2 P71 INT1 P70 I...

Page 39: ...5 O O PORT6 Common driver pins of LCD drivers Common driver pins of LCD drivers Shared with PORT6 SEG0 SEG39 SEG40 SEG43 SEG44 SEG51 SEG52 SEG59 O O PORT5 O PORT8 O PORT9 Segment driver pins of LCD drivers Segment driver pins of LCD drivers Shared with PORT5 7 4 Segment driver pins of LCD drivers Shared with PORT8 Segment driver pins of LCD drivers Shared with PORT9 PORT9 AS FUNCTION KEY CAN WAKE ...

Page 40: ...gh Also see the following table ENTCC I TCC control pin with internal pull high 560KΩ TCC works normally when ENTCC is high and TCC counting is stopped when ENTCC is low MCLK I Input pin for main clock selection Internal pull low through a register CWFS I Minimum access frequency range for call waiting CAS tone Frequency range is 0 5 if CWFS is low Frequency range is 1 5 if CWFS is high R32k I R5 ...

Page 41: ...PS3 PS2 PS1 PS0 Program memory page Address 0 0 0 0 0 Page 0 0 0 0 0 1 Page 1 0 0 0 1 0 Page 2 0 0 0 1 1 Page 3 1 1 1 0 1 Page 29 1 1 1 1 0 Page 30 1 1 1 1 1 Page 31 User can use PAGE instruction to change page To maintain program page by user Otherwise user can use far jump FJMP or far call FCALL instructions to program user s code And the program page is maintained by EMC s complier It will chan...

Page 42: ..._________________________ This specification is subject to change without notice 41 12 19 2005 V2 1 CLK 3 4 1 2 3 4 1 2 3 INSEND Tdiea Tdiei Tiew Tdca CA14 0 Tacc Tcds CD12 0 Tcdh CLK 3 4 1 2 3 4 1 2 3 INSEND Tdiea Tdiei Tiew Tdca CA14 0 Tacc Tcds CD7 0 Tcdh CA 1 HIGH ORDER DATA LOW ORDER DATA ERS 0 CA 1 0 HIGH ORDER DATA CA 1 1 LOW ORDER DATA ERS 1 CA 1 DISABLE Tdca 1 ...

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