eSE Series
2
•
Pad Diagrams (V1.1) 01.17.2005
(These diagrams are subject to change without further notice)
2 eSE005 Pad Diagram
VO2
VSSC
VO1
(0,0)
eSE005
3
4
5
6
7
8
9
10
11
12
13
OSCI
VSSD
P2.0
P2.1
P3.2
P3.3
VD
D
VCC
Pin No.
Symbol
X
Y
Pin No.
Symbol
X
Y
1 NC
10 P2.1
-105.4
-354.4
2 NC
11 P2.0
21.0
-354.4
3 VCC
-544.0
399.1 12 VSSD
158.6
-354.4
4 VO2
-544.0
279.1 13 OSCI
299.0
-352.4
5 VSSC
-544.0
159.1 14 NC
6 VO1
-524.0
39.1 15 NC
7 VDD
-489.8
-351.1 16 NC
8 P3.3
-348.4
-354.4 17 NC
9 P3.2
-226.9
-354.4 18 NC
Chip size
:
1400 * 1050
µ
m
For PCB layout, IC substrate must be connected to VSS (negative power).
NOTE:
1. VO should be floating or connected to VDD (positive power) when not in use.
2. VSSD (negative power) & VSSC should be connected together with negative power.
3. VCC & VDD should be of the same level with the positive power voltage.