eSE Series
Pad Diagrams (V1.1) 01.17.2005
•
3
(These diagrams are subject to change without further notice)
3 eSE007 Pad Diagram
VO2
VSSC
VO1
(0,0)
eSE007
4
5
6
7
8
9
10
11
12
13
14
OSCI
VSSD
P2.0
P2.1
P3.2
P3.3
VDD
VCC
Pin No.
Symbol
X
Y
Pin No.
Symbol
X
Y
1 NC
9 P3.3
-28.0
-378.4
2 NC
10 P3.2
96.7
-378.4
3 NC
11 P2.1
221.4
-378.4
4 VCC
-632.4
-27.9 12 P2.0
346.1
-378.4
5 VO2
-632.4
-147.9 13
VSSD
475.8
-363.4
6 VSSC
-632.4
-267.9 14 OSCI
624.8
-378.4
7 VO1
-612.4
-387.9 15 NC
8 VDD
-148.0
-363.4 16 NC
Chip size
:
1560 * 1100
µ
m
For PCB layout, IC substrate must be connected to VSS (negative power).
NOTE:
1. VO should be floating or connected to VSS (negative power) when not in use.
2. VSSD & VSSC should be connected together with negative power.
3. VCC & VDD should be of the same level with the positive power voltage.
