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Link Layer Tests
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Between 300ns – 900ns elapses between the start of Examiner U1 Exit LFPS and
the start of the PUT U1 Exit LFPS.
The PUT U1 Exit LFPS duration is within 600ns – 900ns.
The test passes if all transactions are correct, no extra packets or LFPS signals
are received, and the PUT enters Recovery.
8.
After Examiner completes this test case, clear the U1/U2 registers through the CV prompt.
Specification Reference
Sections 7.2.4.2.2#1 ● 7.2.4.2.3#1,3,4,5,7,8 ● 7.2.4.2.7#2,3 ● 7.5.7.1#2 ● 7.5.7.2#6
7.19
Low Power Initiation for U2 Test (Downstream
Port Only)
Test Summary
This test verifies that the PUT initiates U2 state.
Test Steps and Expected Results
1.
Examiner performs steps 1 to 4 of TD7.1 (Link Bring-Up Test) to bring the link to U0.
2.
Examiner application prompts the test operator to enable and configure the U1 and U2
inactivity timers through USB30CV. CV will set the U1 Timeout field to 00h and the U2
Timeout field to 7Fh.
3.
Examiner waits to receive LGO_U2 from the PUT.
4.
Examiner transmits an LXU, when it receives the LGO_U2.
The test fails if the PUT sends LPMA.
5.
Examiner waits to receive LGO_U2 from the PUT again.
6.
Examiner transmits an LAU, when it receives the LGO_U2.
The test fails if the PUT does not send LPMA.
The test fails if the PUT does not transition to U2.
