Link Layer Tests
| 85 of 124
S
u
pe
rS
pe
ed
U
S
B
Ex
pl
o
re
r
2
8
0
3.
Examiner waits to receive an LGO_U3 from the PUT.
4.
Examiner sends an LAU when it receives the LGO_U3 from the PUT.
5.
Examiner waits to receive an LPMA from the PUT.
The test fails if Examiner does not receive an LGO_U3, LPMA, or fails to
transition to U3.
6.
Examiner prompts the test operator to Reset the PUT through USB30CV and then hit “OK”.
7.
Examiner waits to receive a Warm Reset LFPS from PUT.
The test fails if no Warm Reset LFPS is received by Examiner before the test
operator hits “OK”.
8.
When Examiner receives a Warm Reset LFPS, the prompt is closed automatically.
9.
Examiner transitions to Rx.Detect.Reset for the duration of the Warm Reset LFPS.
10.
Examiner transitions to Rx.Detect and Examiner and PUT transition through Polling to U0.
The test passes if all exchanges are correct and the link stays in U0 for 50ms.
Specification Reference
Sections 7.2.4.2.4#1,4,5 ● 7.5.9.2#2
7.36
Exit U3 Test (Host Downstream Port Only)
Test Summary
This test verifies that a downstream port initiates U3 Exit with a U3 Exit LFPS.
The operator must install the Product-Specific host controller driver to
perform this test. This TD cannot be tested with the CV compliance driver.
Test Steps and Expected Results
1.
Perform the Link Initialization Sequence to bring Examiner and PUT link to U0.
