Embedian, Inc.
48
SMARC-iMX8MM Computer on Module User’s Manual
v. 1.2
2.1.9.
PCIe_A
Interface
The
SMARC
‐
iMX8MM
offers
one
PCI
Express
x1
lanes.
The
PCIe
signals
are
routed
from
the
NXP®
i.MX8M
Mini
processor
to
the
PCI
Express
port
A
of
the
SMARC
‐
iMX8M
M
edge
finger.
These
signals
support
PCI
Express
Gen.
2.0
interfaces
at
5
Gb/s
and
are
backward
compatible
to
Gen.
1.1
interfaces
at
2.5
Gb/s.
Diodes
PI6CFGL201B
clock
generators
are
used
on
PCIe_A
port
to
make
PCIe
reference
clock
HCSL
signals.
The
following
figure
shows
the
PCIE
port
A
and
B
block
diagram.
Figure
6.
PCI
Express
Block
Diagram
