ENL-Q6391M2
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4.2 Pin Definition
Top side
NO
Name
Type
Description
Voltage
1
GND1
-
Ground
3
NC
-
5
NC
-
7
GND2
-
Ground
9
NC
-
11
NC
-
13
NC
-
15
NC
-
17
NC
-
19
NC
-
21
NC
-
23
NC
-
33
GND3
-
Ground
35
PERP0
I
PCIe
RX
differential
signals
37
PERN0
I
39
GND4
-
Ground
41
PETP0
O
PCIe TX differential signals
43
PETN0
O
45
GND5
-
Ground
47
REFCLKP0
I
PCIe
clock
differential
input signal
49
REFCLKN0
I
51
GND6
Ground
53
CLKREQ0#(I/O)(0/3.3V)
O
PCIe
reference
clock
request signal, open drain,
active low
3.3V
55
PEWAKE0#(I/O)(0/3.3V)
O
PCIe wake up host, open
drain, active low
3.3V
57
GND7
-
Ground
59
RESERVED_PERP1
-
NC
61
RESERVED_PERN1
-
NC
63
GND8
-
Ground
65
RESERVED_PETP1
-
NC