Service Manual
Operating Principles
2.2.1.3 Interrupt Control
The
deterrnines the priority level of the interrupt and outputs it to terminals
-
Then an interrupt is sent to the CPU. When the
value is
the CPU process is a
interrupt process. When the
value is
the CPU process is a standard
process. When the
is any other value, the CPU process is a rnaskable interrupt process.
2.2.1.4
DRAM Management
The
video controller uses DRAMs for the system RAM and for the V-RAM.
In this printer, a standard four 512K x DRAMs are mounted in locations
and
providing a total of 2.0 MB. SIMM sockets number
and number 2
are optional
SIMM sockets. These SIMM sockets can use 1,2,4,8,16,32 MB SIMM (32-bit bus).
The DRAMs (including optional
are managed by the
E05A91. The
handles the management. The
outputs MAO-10 (memory address),
and WE
signals.
DWE
CAS0,1,2,3
MAO-10
r
I
Standard
DRAM
SIMM
slot 1,2
CPU Data
Bus
Figure 2-40. DRAM Management
Rev.
2-27
