Epson RX-8564LC Applications Manual Download

Page: 18 / 39

−

8564

Page

−

ETM12E-01

13.1.4. Calendar counter

(

Reg

−

[h]

)

Address

[h]

Function

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Days

Months / Century

Years

•

The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.

•

The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.

∗

Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.

1) [

Day

]

(

Reg

−

[h]

)

•

This is the date counter.

Updating of this counter varies depending on the month.

∗

A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In

February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc.

[

Days

]

Month

Date update pattern

1, 3, 5, 7, 8, 10, or 12

01, 02, 03

∼

30, 31, 01

∼

4, 6, 9, or 11

01, 02, 03

∼

30, 01, 02

∼

February in normal year

01, 02, 03

∼

28, 01, 02

∼

Write / Read

February in leap year

01, 02, 03

∼

28, 29, 01

∼

2) [

Months

Century

]

(

Reg

−

[h]

)

•

This is the month counter.

It is updated in annual cycles of regularly ordered months (January, February, March, etc.).

3) [

YEAR

]

(

Reg

−

[h]

)

•

This is the year counter.

It is updated in 100-year cycles of regularly ordered years (00, 01, 02 to 99, etc.).

∗

Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.

4) C bit

(

Century bit

)

•

This bit indicates change of century.

∗

When the year digit data overflows from 99 to 00, this bit is set. By presetting it to 0 while still in the 20th

century, it will be set in year 2000, but in fact the first year in the 21 century should be 2001.

13.1.5. Day counter

(

Reg

−

6[h]

)

Address

[h]

Function

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Weekdays

•

The day (of the week) is indicated by 3 bits, bit 0 to bit 2.

[

Weekdays

]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Day

Sunday

Monday

Tuesday

Wednesday

Thursday

Friday

Write

Read

Saturday

∗

Note with caution that any settings other than the seven listed above may prevent normal operation.

Summary of Contents for RX-8564LC

Page 1: ...RM0403 3 E01 Application Manual Real Time Clock Module RX 8564LC Model Product Number RX 8564LC Q418564C0xxxx00 ...

Page 2: ...ency These products are intended for general use in electronic equipment When using them in specific applications that require extremely high reliability such as applications stated below it is required to obtain the permission from EPSON TOYOCOM in advance Space equipment artificial satellites rockets etc Transportation vehicles and related automobiles aircraft trains vessels etc Medical instrume...

Page 3: ...egisters 10 12 1 Overview of Functions 10 12 2 Register table 11 13 Description of Functions 12 13 1 Description of registers 12 13 1 1 Control register 1 Reg 00 h 12 13 1 2 Control register 2 Reg 01 h 13 13 1 3 Clock counter Reg 02 h to 04 h 14 13 1 4 Calendar counter Reg 05 h 07 h 08 h 15 13 1 5 Day counter Reg 6 h 15 13 1 6 Alarm registers Reg 09 h to 0C h 16 13 1 7 Timer setting register Reg 0...

Page 4: ...t in 32 768 kHz crystal oscillator In addition to a calendar year month day weekday hour minute second function and a clock counter function this module s real time clock functions include an alarm function and a fixed cycle timer interrupt function The devices in this module are fabricated via a C MOS process for low current consumption which enables long term battery back up All of these many fu...

Page 5: ...D0 bit to control the output mode of the CLKOUT output pin The CLKOE input pin can be used in combination with the FE bit FD1 bit and FD0 bit to select the frequency output from the CLKOUT output pin 32 768 kHz 1024 Hz 32 Hz or 1 Hz or to stop output When output is stopped the CLKOUT output pin is at low level L CLKOE pin input FE bit CLKOUT pin output 1 Output C MOS H 0 OFF L 1 OFF L L 0 OFF L Du...

Page 6: ...soldering pattern Unit mm 0 4 2 8 0 2 2 77 0 8 1 6 0 8 3 2 0 27 0 5 2 4 2 5 Min 0 1 1 0 1 0 08 2 4 12 7 1 6 0 5 0 22 0 08 M 3 6 0 2 4 2 Marking Layout RX 8564 LC VSOJ 12pin 1 Pin Mark Logo Production lot E 8564 A123B Type Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning ...

Page 7: ...PR No condensation 40 to 85 C 1 See 8 1 DC Electrical Characteristics 7 Frequency Characteristics Unless otherwise specified GND 0 V Ta 25 C VDD 3 0 V Item Symbol Comments Min Typ Max Unit Output frequency fo 32 768 Typ kHz Frequency precision f f Ta 25 C VDD 3 0 V 5 23 1 2 10 6 Frequency voltage characteristics f V Ta 25 C VDD 1 8 V to 5 5 V 2 Max 10 6 V Frequency temperature characteristics Top ...

Page 8: ... Hz VDD 2 0 V 250 650 nA fSCL 0 Hz VDD 5 0 V 2 5 3 4 µA fSCL 0 Hz VDD 3 0 V 1 5 2 2 µA Current consumption interface inactive fSCL 0 Hz CLKOUT 32 kHz output LOAD is 0 pF IDD32K fSCL 0 Hz VDD 2 0 V 1 1 1 6 µA L input voltage VIL GND 0 5 0 3 VDD V H input voltage VIH 0 7 VDD VDD 0 5 V L output current IOL SDA VOL 0 4 V VDD 5 V 3 mA L output current IOL INT VOL 0 4 V VDD 5 V 1 mA L output current IOL...

Page 9: ... 0 6 µs Bus free time between a STOP and START condition tBUF 1 3 µs SCL L time tLOW 1 3 µs SCL H time tHIGH 0 6 µs SCL and SDA rise time tr 0 3 µs SCL and SDA fall time tf 0 3 µs Tolerance spike time on bus tSP 50 ns Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P ...

Page 10: ...voltage characteristics f f f fo fT fV f f Clock accuracy stable frequency in any temperature and voltage f fo Frequency precision fT Frequency deviation in any temperature fV Frequency deviation in any voltage 3 How to find the date difference Date Difference f f 86400 Sec For example f f 11 574 10 6 is an error of approximately 1 second day 2 Current and voltage consumption characteristics 2 1 C...

Page 11: ...RX 8564 LC Page 8 ETM12E 01 10 External connection example device SCL SDA GND VDD Master VDD SCL SDA t r R CBUS Pull up Registor 8564 SCL SDA GND VDD SLAVE ADRS 1010001 I C BUS 2 I C BUS 2 ...

Page 12: ...ime before mounting this device Also check again if the mounting conditions are later changed See Fig 2 profile for our evaluation of Soldering heat resistance for reference 2 Packaging equipment This product uses a molded package whose back contains glass Therefore it is possible for shocks during packaging to cause product breakage depending on the packaging machinery and conditions Please be su...

Page 13: ...level L and 1 is set to the TF bit to report that an event has occurred Two types of operations can be selected for this function level interrupt mode and repeated interrupt mode For details see 13 2 Fixed cycle Interrupt Function 3 Alarm interrupt function The alarm interrupt generation function generates interrupt events for alarm settings such as date day hour and minute settings When an interr...

Page 14: ...oid setting incorrect data as the date or time as timed operations cannot be guaranteed if incorrect date or time data has been set 1 During the initial power on from 0 V the power on reset function sets 1 to the VL bit Since the value of other registers is undefined at this time be sure to reset all registers before using them 2 During the initial power on from 0 V the power on reset function set...

Page 15: ...he clock calendar alarm timer etc 1 When the STOP bit 1 operations are restricted Do not use any settings other than the clock and calendar settings 2 When the STOP bit 1 output via CLKOUT may be stopped depending on the selected frequency Note this with caution 1 If 32 768 kHz has been selected as the output frequency output will continue at 32 768 kHz 2 If any other output frequency was selected...

Page 16: ...pt Function 3 TF bit Timer Flag This is a flag bit that retains the result when a fixed cycle timer interrupt event has been detected When a fixed cycle timer interrupt event occurs this bit s value changes from 0 to 1 For details see 9 2 Fixed cycle Timer Interrupt Function 4 AIE bit Alarm Interrupt Enable This bit sets the operation of the INT interrupt signal when an alarm interrupt event has o...

Page 17: ...ow Flag This is a flag bit that retains the result when detecting low voltage When the power source s voltage drops below VLOW V this flag is set to 1 If this bit s value is 1 when read this RTC s data is ignored in which case all registers should be initialized before being used 1 A 1 is set to this VL flag during initial power on from 0 V Since the value of other registers is undefined at this t...

Page 18: ...r 01 02 03 28 01 02 Write Read February in leap year 01 02 03 28 29 01 2 Months Century register Reg 07 h This is the month counter It is updated in annual cycles of regularly ordered months January February March etc 3 YEAR register Reg 08 h This is the year counter It is updated in 100 year cycles of regularly ordered years 00 01 02 to 99 etc Any year that is a multiple of four 04 08 12 88 92 96...

Page 19: ...t the fixed cycle timer interrupt function starts operating When 0 is written to this bit the fixed cycle timer interrupt function stops operating For details see 9 2 Fixed cycle Timer Interrupt Function 2 TD1 TD0 bits Timer countDown interval select 1 0 These bits specify the fixed cycle timer interrupt function s countdown period source clock Four different periods can be selected via combinatio...

Page 20: ...it When the FE bit value is 0 the CLKOUT pin is output STOP mode low level 2 FD1 FD0 bits A combination of the FD1 and FD0 bits is used to select the frequency to be output 3 CLKOUT output based on various settings CLKOE pin input FE bit FD1 bit FD0 bit CLKOUT pin output 0 0 32768 Hz Output C MOS 0 1 1024 Hz Output C MOS 1 0 32 Hz Output C MOS 1 1 1 1 Hz Output C MOS H 0 Χ Χ OFF L 1 Χ Χ OFF L L 0 ...

Page 21: ... indicates when a fixed cycle timer interrupt event has occurred changes from 0 to 1 2 When the TIE Timer Interrupt Enable bit value is 1 the INT output pin status changes from Hi Z to L 1 Overview of level interrupt mode TI TP bit 0 Once an interrupt event has occurred the operation ends after one iteration However if only the TF bit is cleared to zero without stopping operation of the fixed cycl...

Page 22: ...ated interrupt mode 3 The timer s down counter automatically returns to the preset value and then the countdown operation is repeated When the TE bit value is 1 countdown operation of the timer s down counter will be repeated regardless of the operation mode or of any event that has occurred 4 When the TE bit is cleared from 1 to 0 the fixed cycle timer interrupt function stops 1 The TF bit value ...

Page 23: ...imer countDown interval select 1 0 These bits specify the fixed cycle timer interrupt function s countdown period source clock Four different periods can be selected via combinations of these two bit values INT auto recovery time tRTN during repeated interrupt mode TD1 TD0 TD1 bit 1 TD0 bit 0 Source clock Preset value n 1 Preset value 1 n 0 0 4096 Hz 244 14 µs cycle 122 µs 244 µs 0 1 64 Hz 15 625 ...

Page 24: ...to start TE Data Description 0 Stops fixed cycle timer interrupt function Write Read 1 Starts fixed cycle timer interrupt function 5 TF bit Timer Flag This is a flag bit that retains the result when a fixed cycle timer interrupt event is detected If it was already cleared to zero this value changes from 0 to 1 when an event occurs and the new value is retained TF Data Description 0 The TF bit is c...

Page 25: ...on of the source clock settings settings in TD1 and TD0 and fixed cycle timer countdown setting Reg C setting sets the fixed cycle timer interrupt interval as shown in the following examples Source clock Timer Counter setting 4096 Hz TD1 0 0 0 64 Hz TD1 0 0 1 1 Hz When seconds setting is updated TD1 0 1 0 1 60 Hz When minutes setting is updated TD1 0 1 1 0 00h 1 01h 244 14 µs 15 625 ms 1 s 1 min 2...

Page 26: ...leared set to operation stop mode to prevent hardware interrupts from occurring inadvertently while entering settings 1 When the TE bit value is changed from 0 to 1 the fixed cycle timer s countdown begins 2 A fixed cycle timer interrupt event occurs when the down counter value goes from 01h to 00h during a countdown in which the down counter s count value is decremented at each source clock cycle...

Page 27: ...at all control related bits are zero cleared set to operation stop mode to prevent hardware interrupts from occurring inadvertently while entering settings 1 When the TE bit value is changed from 0 to 1 the fixed cycle timer s countdown begins 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 01h to 00h an interrup...

Page 28: ...d date at which an alarm interrupt event will occur is set in advance and the interrupt event occurs when the current time matches this pre set time 2 When a time alarm interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occurs INT...

Page 29: ...ject to any comparison that would trigger an alarm interrupt To exclude a setting from possibly triggering an alarm interrupt write 1 to the AE bit in the register corresponding to the setting in question Example To leave hour minute and day of week weekday settings as possible alarm interrupt triggers while excluding only the day setting from being a possible alarm interrupt trigger Write 80h AE ...

Page 30: ... has occurred without having to set the INT pin to low level monitor the AF bit value to see if it changes from 0 to 1 while keeping the AIE bit value as 0 13 3 3 Examples of alarm settings 1 Basic information about alarm settings Four parameters can be set as alarm objects minute hour day and date Hour settings are based on a 24 hour clock To exclude a setting from possibly triggering an alarm in...

Page 31: ...nterrupt function When an interrupt occurs when INT is at low level L read the TF and AF flags to determine which type of interrupt event occurred which flag value changed to 1 2 How to prevent INT pin from going to low level L To prevent the INT pin from going to low level L clear all TIE and AIE bits to zero To detect when an interrupt event has occurred without having to set the INT pin to low ...

Page 32: ...setting refer to Write to clock and calendar below Set alarm interrupt Set the alarm interrupt function Reg 09 h to 0C h If the alarm interrupt function is not being used we recommend writing 1 to all four AE bits Set CLKOUT output Set the CLKOUT output pin s output status Reg 0D h Since the initial power on setting is output 32 768 kHz clock write 0 to the FE bit to stop output Set timer interrup...

Page 33: ...cess Set current time STOP 1 Write 1 to the STOP bit to prevent clock updates while setting the current time Write current time Write the data among the Year Month Day day of week hour minute second data that needs to be set or reset When initializing be sure to initialize all of the data STOP 0 Zero clear the STOP bit to start restart the clock s operation The clock starts from the set second 500...

Page 34: ...e to set or reset the down counter s initial value see 3 above Set TI TP bit 1 Select the operation mode one shot interrupt or repeated continuous interrupts 1 When repeated continuous interrupts are selected Write 1 to the TI TP bits 2 When one shot interrupt is selected Write 0 to the TI TP bits 1 Set TIE bit 2 Select event triggered INT output output do not output interrupt when at low level 1 ...

Page 35: ... its slave address matches the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse 13 6 2 System configuration All ports connected to the I 2 C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line via a pull up resistance...

Page 36: ...opped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 1 seconds A RESTART condition may be sent between a START condition and STOP condition but even in such cases...

Page 37: ...e corresponding to the 8th bit of data on the SCL line the transmitter releases the SDA line and the receiver sets the SDA line to low acknowledge level SCL from Master SDA from transmitter sending side ACK signal 1 2 8 9 SDA from receiver receiving side Release SDA Low active After transmitting the ACK signal if the Master remains the receiver for transfer of the next byte the SDA is released at ...

Page 38: ...564 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers 8564 s slave address with the R W bit set to read mode 8 Check for ACK signal from 8564 from this point on the CPU is the receiver and the 8564 is the transmitter 9 Data from address specified at 4 above is output by the 8564 10 CPU transfers ACK signal to 8564 11 Repeat 9 and 10 if nece...

Page 39: ...hoehe 5 40822 Mettmann Germany Phone 49 2104 91890 Fax 49 2104 918930 UK Office Unit 4 e space south 26 St Thomas Place Ely Cambridgeshir CB7 4EX England Phone 44 0 1353 644060 Fax 44 0 8704 583822 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSangHuan ChaoYang District Beijing China Phone 86 10 6410 6655 Fax 86 10 6410 7319 http www epson com cn Shinghai Branch High Tech Buildin...

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