S1C63656 TECHNICAL MANUAL
EPSON
85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.11 Programming notes
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,
the high-order 4 bits (PTDx4–PTDx7) are not latched when the low-order 4 bits are read. Therefore,
the high-order 4 bits should be read within 0.73 msec (when f
OSC1
is 32.768 kHz) from reading the
low-order 4 bits. When the CPU is running with the OSC1 clock and the programmable timer is
running with the OSC3 clock, stop the timer before reading the counter data. The counter running
with OSC3 counts down for the value listed in Table 4.10.11.1 while the CPU running with OSC1 reads
the low-order 4 bits and high-order 4 bits of the counter data by two instructions.
Table 4.10.11.1 Counter change with OSC3 between readings low-order and high-order data with OSC1
Count clock
OSC3/1
OSC3/4
OSC3/32
Counter change between reading
0200H
001AH
0002H
In 16-bit mode, the counter data must be read in the order below.
PTD00–PTD03
→
PTD04–PDT07
→
PTD10–PTD13
→
PTD14–PTD17
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The
PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 4.10.11.1 shows the timing chart for the RUN/STOP control.
PTRUNx (WR)
PTDx0–PTDx7
42H
41H 40H 3FH 3EH
3DH
PTRUNx (RD)
Input clock
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 4.10.11.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
