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Epson Research and Development

Page 21

Vancouver Design Center

S5U13504B00C Rev. 2.0 PCI Evaluation Board User Manual

S1D13504

Issue Date: 2002/12/02

X19A-G-014-01

4.4 Current Consumption Measurement

The evaluation board has 2 headers, JP3 and JP4, which allow the independent
measurement of S1D13504 CoreVDD and IOVDD current consumption. To measure the
current, remove the appropriate jumper and connect an ammeter to the corresponding
header pins.

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Summary of Contents for S1D13504

Page 1: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 2: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 TECHNICAL MANUAL X19A Q 002 14 Issue Date 01 04 18 THIS PAGE LEFT BLANK ...

Page 3: ...To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4...

Page 4: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 TECHNICAL MANUAL X19A Q 002 14 Issue Date 01 04 18 THIS PAGE LEFT BLANK ...

Page 5: ...me passive LCD interface 4 8 16 bit color passive LCD interface Single panel single drive displays Dual panel dual drive displays Direct support for 9 12 bit TFT 18 bit TFT is sup ported up to 64K color depth 16 bit data External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus Simultaneous display of CRT and 4 8 bit passive or 9 bit TFT panels regardless of re...

Page 6: ... 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 ...

Page 7: ...ocument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Ep...

Page 8: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 THIS PAGE LEFT BLANK ...

Page 9: ...nctional Block Descriptions 17 4 2 1 Host Interface 17 4 2 2 Memory Controller 17 4 2 3 Display FIFO 17 4 2 4 Look Up Table 17 4 2 5 LCD Interface 17 4 2 6 Power Save 17 5 Pin Out 18 5 1 Pinout Diagram for S1D13504F00A 18 5 2 Pinout Diagram for S1D13504F01A 19 5 3 Pinout Diagram for S1D13504F02A 20 5 4 Pin Description 21 5 4 1 Host Interface 21 5 4 2 Memory Interface 24 5 4 3 LCD Interface 26 5 4 ...

Page 10: ...ing 61 7 4 Display Interface 62 7 4 1 Power On Reset Timing 62 7 4 2 Suspend Timing 63 7 4 3 Single Monochrome 4 Bit Panel Timing 64 7 4 4 Single Monochrome 8 Bit Panel Timing 66 7 4 5 Single Color 4 Bit Panel Timing 68 7 4 6 Single Color 8 Bit Panel Timing Format 1 70 7 4 7 Single Color 8 Bit Panel Timing Format 2 72 7 4 8 Single Color 16 Bit Panel Timing 74 7 4 9 Dual Monochrome 8 Bit Panel Timi...

Page 11: ...Manipulation 117 11 Clocking 118 11 1 Maximum MCLK PCLK Ratios 118 11 2 Frame Rate Calculation 119 12 Look Up Table Architecture 121 12 1 Gray Shade Display Modes 121 12 2 Color Display Modes 123 13 Power Save Modes 127 13 1 Hardware Suspend 127 13 2 Software Suspend 127 13 3 Power Save Mode Function Summary 128 13 4 Pin States in Power Save Modes 128 14 Mechanical Data 129 14 1 QFP15 128 S1D13504...

Page 12: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 THIS PAGE LEFT BLANK ...

Page 13: ...ace Timing 37 Table 7 2 MC68K Bus 1 Interface Timing 39 Table 7 3 MC68K Bus 2 Interface Timing 41 Table 7 4 Generic MPU Interface Synchronous Timing 43 Table 7 5 Generic MPU Interface Asynchronous Timing 45 Table 7 6 Clock Input Requirements 46 Table 7 7 EDO DRAM Read Timing 47 Table 7 8 EDO DRAM Write Timing 49 Table 7 9 EDO DRAM Read Write Timing 51 Table 7 10 EDO DRAM CAS Before RAS Refresh Tim...

Page 14: ...election 95 Table 8 6 Simultaneous Display Option Selection 96 Table 8 7 Number of Bits Per Pixel Selection 97 Table 8 8 Pixel Panning Selection 100 Table 8 9 PCLK Divide Selection 101 Table 8 10 Suspend Refresh Selection 101 Table 8 11 Minimum Memory Timing Selection 107 Table 8 12 RAS to CAS Delay Timing Select 108 Table 8 13 RAS Precharge Timing Select 108 Table 8 14 Optimal NRC NRP and NRCD Va...

Page 15: ... DRAM Read Write Timing 50 Figure 7 10 EDO DRAM CAS Before RAS Refresh Timing 52 Figure 7 11 EDO DRAM Self Refresh Timing 53 Figure 7 12 FPM DRAM Read Timing 54 Figure 7 13 FPM DRAM Write Timing 56 Figure 7 14 FPM DRAM Read Write Timing 58 Figure 7 15 FPM DRAM CAS Before RAS Refresh Timing 60 Figure 7 16 FPM DRAM CBR Self Refresh Timing 61 Figure 7 17 LCD Panel Power On Reset Timing 62 Figure 7 18...

Page 16: ...zation 115 Figure 10 2 15 16 Bit Per Pixel Format Memory Organization 116 Figure 10 3 Image Manipulation 117 Figure 12 1 1 Bit Per Pixel 2 Level Gray Shade Mode Look Up Table Architecture 121 Figure 12 2 2 Bit Per Pixel 4 Level Gray Shade Mode Look Up Table Architecture 122 Figure 12 3 4 Bit Per Pixel 16 Level Gray Shade Mode Look Up Table Architecture 122 Figure 12 4 1 Bit Per Pixel 2 Level Color...

Page 17: ... us via email at documen tation erd epson com 1 2 Overview Description The S1D13504 is a low cost low power color monochrome LCD CRT controller interfacing to a wide range of CPUs and LCDs The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where Windows CE may serve as a primary oper...

Page 18: ... for minimum wait state CPU writes Registers are memory mapped M R pin selects between memory and register address space The complete 2M byte display buffer address space is directly and contiguously available through the 21 bit address bus 2 3 Display Support 4 8 bit monochrome or 4 8 16 bit color passive LCD interface for single panel single drive displays 8 bit monochrome or 8 16 bit color pass...

Page 19: ...d instantaneous screen update Fast Update feature accelerates screen update by allocating full display buffer bandwidth to CPU see REG 23h bit 7 2 5 Clock Source Single clock input for both pixel and memory clocks Memory clock can be input clock or input clock 2 this provides flexibility to use CPU bus clock as input clock Pixel clock can be memory clock memory clock 2 memory clock 3 or memory clo...

Page 20: ...7 0 4 8 16 bit LCD Display SH 3 BUS RESET WE0 D 15 0 BS RD WR RD WAIT A 20 0 CKIO WE0 RD WR AB 20 0 DB 15 0 WE1 BS RD M R CS BUSCLK SUSPEND WAIT RESET A21 CSn WE1 LCDPWR WE A 11 0 D 15 0 RAS 1Mx16 LCAS UCAS MA 11 0 MD 15 0 WE RAS LCAS UCAS FPM EDO DRAM Power Management S1D13504 FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16 bit LCD ...

Page 21: ...splay MC68030 BUS RESET SIZ0 D 31 16 AS R W SIZ1 DSACK1 A 20 0 BCLK WE0 RD WR AB 20 0 DB 15 0 WE1 BS RD M R CS BUSCLK SUSPEND WAIT RESET A 31 21 FC0 FC1 Decoder Decoder DS LCDPWR WE A 8 0 D 15 0 RAS 256Kx16 LCAS UCAS MA 8 0 MD 15 0 WE RAS LCAS UCAS FPM EDO DRAM Power Management S1D13504 FPFRAME FPSHIFT FPLINE DRDY FPDAT 15 8 FPDAT 7 0 CLKI Oscillator FPFRAME FPSHIFT FPLINE MOD UD 7 0 LD 7 0 4 8 16...

Page 22: ...002 19 Issue Date 01 11 06 4 Block Description 4 1 Functional Block Diagram Figure 4 1 System Block Diagram Showing Datapaths LCD Memory Controller 16 bit FPM EDO DRAM LCD Clocks Power Save Register CRTC Look Up I F CPU MPU Host I F DAC CPU R W Bus Clock Memory Clock Pixel Clock Display FIFO Control DAC Data Table ...

Page 23: ... as generates the necessary signals to interface to one of the supported 16 bit memory devices FPM DRAM or EDO DRAM 4 2 3 Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh 4 2 4 Look Up Table The Look Up Table block contains three 16x4 Look Up Tables one for each primary color In monochrome mode only one of these Look Up Tables is selected and ...

Page 24: ...97 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 58 59 60 61 62 63 51 52 53 54 55 56 57 64 S1D13504F00A RD WR WAIT IOVDD VSS DB15 DB14 DB12 DB8 DB5 DB3 DB2 DB1 DB0 DB13 DB4 AB2 RESET COREVDD MA6 MA8 DB7 FPDAT3 MA3 MA4 MA2 MA5 MD6 MA11 MA0 MA7 MA10 MA9 IOVDD VRTC DACCLK HRTC DACRS1 DACRS0 FPDAT13 FPDAT10 RAS WE UCAS VSS MD7 MD8 MD5 MD10 MD4 MD11 MD3 MD12 MD2 MD13 MD1 AB3 IOVDD BS WE1 WE0 RD...

Page 25: ... 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 58 59 60 61 62 63 51 52 53 54 55 56 57 64 S1D13504F01A RD WR WAIT IOVDD VSS DB15 DB14 DB12 DB8 DB5 DB3 DB2 DB1 DB0 DB13 DB4 AB2 RESET COREVDD MA6 MA8 DB7 FPDAT3 MA3 MA4 MA2 MA5 MD6 MA11 MA0 MA7 MA10 MA9 IOVDD VRTC DACCLK HRTC DACRS1 DACRS0 FPDAT13 FPDAT10 RAS WE UCAS VSS MD7 MD8 MD5 MD10 MD4 MD11 MD3 MD12 MD2 MD13 MD1 AB3 IOVDD BS WE1 WE0 RD M R ...

Page 26: ...AT14 VSS MD14 DB10 DB9 VSS DB11 DB6 MA1 LCAS MD9 FPDAT5 FPDAT7 DACRD BLANK VSS FPDAT8 MD0 FPDAT9 FPDAT12 FPDAT0 FPDAT1 FPDAT11 FPDAT6 GPIO0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC NC NC NC 108107 1061051041031021011009...

Page 27: ...6 3mA 3 12 6mA Table 5 1 Host Interface Pin Descriptions Pin Name Type Pin Driver Reset 0 Value Description F00A F01A F02A AB0 I 3 5 CS Hi Z This pin has multiple functions For SH 3 mode this pin inputs system address bit 0 A0 For MC68K Bus 1 this pin inputs the lower data strobe LDS For MC68K Bus 2 this pin inputs system address bit 0 A0 For Generic Bus this pin inputs system address bit 0 A0 See...

Page 28: ...ping on page 31 BS I 6 8 CS Hi Z This pin has multiple functions For SH 3 mode this pin inputs the bus start signal BS For MC68K Bus 1 this pin inputs the address strobe AS For MC68K Bus 2 this pin inputs the address strobe AS For Generic Bus this pin must be tied to IO VDD See Table 5 9 Host Bus Interface Pin Mapping on page 31 RD WR I 10 12 CS Hi Z This pin has multiple functions For SH 3 mode t...

Page 29: ...This pin has multiple functions For SH 3 mode this pin outputs the wait request signal WAIT MD5 must be pulled low during reset by the internal pull down resistor For MC68K Bus 1 this pin outputs the data transfer acknowledge signal DTACK MD5 must be pulled high during reset by an external pull up resistor For MC68K Bus 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 MD5 mus...

Page 30: ...er byte UWE See Table 5 10 Memory Interface Pin Mapping on page 32 for summary WE O 48 54 CO1 Output 1 This pin has multiple functions For dual CAS DRAM this is the write enable signal WE For single CAS DRAM this is the write enable signal for the lower byte LWE See Table 5 10 Memory Interface Pin Mapping on page 32 for summary RAS O 47 53 CO1 Output 1 Row address strobe MD 15 0 IO 67 65 63 61 59 ...

Page 31: ...rface Pin Mapping on page 32 for summary MA10 IO 42 48 C TS1 Hi Z Output 01 This pin has multiple functions For asymmetrical 2M byte DRAM this is memory address bit 10 MA10 For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose IO GPIO1 See Table 5 10 Memory Interface Pin Mapping on page 32 for summary MA11 IO 44 50 C TS1 Hi Z Output 01 This pin has multiple fu...

Page 32: ... output The active polarity of this output is selected by the state of MD10 at the rising edge of RESET see Section 5 5 Summary of Configuration Options on page 30 This output is controlled by the power save mode circuitry see Section 13 Power Save Modes on page 127 for details DRDY O 72 82 CN3 Output 0 This pin has multiple functions which are automatically selected depending on panel type used F...

Page 33: ...nctions Write signal for external RAMDAC support General Purpose IO GPIO7 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 DACRS1 IO 101 115 C TS1 Hi Z Output 01 This pin has multiple functions Register Select bit 1 for external RAMDAC support General Purpose IO GPIO9 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 DACRS0 IO 100 114 C TS1 Hi Z Output 01 This pin has mu...

Page 34: ...ge 33 VRTC IO 103 117 C CN3 Hi Z Output 01 This pin has multiple functions Vertical Retrace signal for CRT General Purpose IO GPIO11 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 BLANK IO 85 95 C CN3 Hi Z Output 01 This pin has multiple functions Blanking signal for DAC General Purpose IO GPIO5 See Table 5 11 LCD CRT RAMDAC Interface Pin Mapping on page 33 DACCLK O 86 96 C CN3 Out...

Page 35: ...wer Save Modes on page 127 for details When MD 10 9 01 at rising edge of RESET this pin is an output with a reset state of 0 Its state is controlled by REG 21h bit 7 When MD 10 9 11 at rising edge of RESET this pin is an output with a reset state of 1 Its state is controlled by REG 21h bit 7 GPIO0 IO 12 14 C TS1 Hi Z General Purpose IO pin 0 TSTEN I 107 121 CD Hi Z pulled 0 Test Enable This in sho...

Page 36: ...MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active low 0 insert wait state MD 7 6 Memory Address GPIO configuration 00 symmetrical 256K 16 DRAM MA 8 0 DRAM address MA 11 9 GPIO 2 1 and GPIO3 01 symmetrical 1M 16 DRAM MA 9 0 DRAM address MA 11 10 GPIO 2 1 10 asymmetrical 256K 16 DRAM MA 9 0 DRAM address MA 11 10 GPIO 2 1 11 asymmetrical 1M 16 DRAM MA 11 0 DRAM a...

Page 37: ...K Bus 2 Generic MPU AB 20 1 A 20 1 A 20 1 A 20 1 A 20 1 AB0 A0 LDS A0 A0 DB 15 0 D 15 0 D 15 0 D 31 16 D 15 0 WE1 WE1 UDS DS WE1 M R External Decode External Decode External Decode External Decode CS CSn External Decode External Decode External Decode BUSCLK CKIO CLK CLK BCLK BS BS AS AS Connect to IO VDD RD WR RD WR R W R W RD1 RD RD Connect to IO VDD SIZ1 RD0 WE0 WE0 Connect to IO VDD SIZ0 WE0 W...

Page 38: ...ise should be connected to either VSS or IO VDD if not used Table 5 10 Memory Interface Pin Mapping S1D13504 Pin Names FPM EDO DRAM Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE MD 15 0 DQ 15 0 MA 8 0 A 8 0 MA9 GPIO31 A9 MA10 GPIO11 A10 MA11 GPIO21 A11 UCAS UCAS UWE UCAS UWE UCAS UWE UCAS UWE LCAS LCAS CAS LCAS CAS LCAS CAS LCAS CAS WE WE LWE WE LWE WE L...

Page 39: ...driven 0 D3 D3 LD3 LD3 G2 G3 G5 Note2 FPDAT4 D0 D4 UD0 D0 D4 D4 UD0 UD0 G1 G2 G4 Note2 FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 UD1 G0 G1 G3 Note2 FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 UD2 B2 B3 B5 Note2 FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 UD3 B1 B2 B4 Note2 FPDAT8 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 LD4 B0 B1 B3 Note2 FPDAT9 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 LD5 dri...

Page 40: ... Core VDD Supply Voltage VSS 0 V 2 7 3 0 3 3 3 6 V IO VDD Supply Voltage VSS 0 V 2 7 3 0 3 3 5 0 5 5 V VIN Input Voltage VSS IO VDD V TOPR Operating Temperature 40 25 85 C Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units VIL Low Level Input Voltage CMOS inputs IO VDD 3 0 3 3 5 0 0 8 0 8 1 0 V V V VIH High Level Input Voltage CMOS inputs IO VDD 3 0 3 3 5 0 1 9 2 0 3 5 V V...

Page 41: ...ndition Min Typ Max Units VOL Low Level Output Voltage Type 1 TS1 CO1 TS1D Type 2 TS2 CO2 Type 3 TS3 CO3 IOL 3mA IOL 6mA IOL 12mA 0 4 V VOH High Level Output Voltage Type 1 TS1 CO1 TS1D Type 2 TS2 CO2 Type 3 TS3 CO3 IOL 1 5 mA IOL 3 mA IOL 6 mA IO VDD 0 4 V IOZ Output Leakage Current IO VDD Max VOH VDD VOL VSS 1 1 µA COUT Output Pin Capacitance 10 pF CBID Bidirectional Pin Capacitance 10 pF ...

Page 42: ...ts must be 5 nsec 10 90 CL 50pF Bus MPU Interface CL 100pF LCD Panel Interface CL 10pF Display Buffer Interface CL 10pF CRT DAC Interface 7 1 CPU Interface Timing 7 1 1 SH 3 Interface Timing Figure 7 1 SH 3 Interface Timing Note The SH 3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non zero value t1 t2 t3 t4 t10 t11 t15 t5 t6 t7 t8 t9 t12 t16 t13 t14 CKIO...

Page 43: ...after A 20 0 and M R become valid whichever occurs later Table 7 1 SH 3 Interface Timing Symbol Parameter Min Max Units t1 Clock period 25 ns t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 0 M R RD WR setup to CKIO 4 ns t5 A 20 0 M R RD WR hold from CS 0 ns t6 BS setup 3 ns t7 BS hold 0 ns t8 CSn setup 0 ns t92 Falling edge RD to D 15 0 driven 3 ns t10 Rising edge CSn to WAIT...

Page 44: ...Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 1 2 MC68K Bus 1 Interface Timing e g MC68000 Figure 7 2 MC68K Bus 1 Interface Timing A 20 1 AS UDS D 15 0 write M R R W DTACK CLK t1 t2 t3 t4 t10 t7 CS t6 t9 t5 LDS t11 t12 D 15 0 read t13 t14 t15 t8 t16 ...

Page 45: ...ing Symbol Parameter Min Max Units t1 Clock period 30 ns t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 1 M R setup to first CLK where CS 0 AS 0 and either UDS 0 or LDS 0 4 ns t5 A 20 1 M R hold from AS 0 ns t6 CS hold from AS 0 ns t7 R W setup to before to either UDS 0 or LDS 0 5 ns t8 R W hold from AS 0 ns t91 AS 0 and CS 0 to DTACK driven high 1 ns t10 AS high to DTACK hig...

Page 46: ...dware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 1 3 MC68K Bus 2 Interface Timing e g MC68030 Figure 7 3 MC68K Bus 2 Interface Timing A 20 0 AS DS D 31 16 write SIZ 1 0 M R R W DSACK1 CLK t1 t2 t3 t4 t10 t7 CS t6 t8 t5 D 31 16 read t11 t12 t9 t13 t14 t15 t16 ...

Page 47: ...iming Symbol Parameter Min Max Units t1 Clock period 30 ns t2 Clock pulse width high 5 ns t3 Clock pulse width low 5 ns t4 A 20 0 SIZ 1 0 M R setup to first CLK where CS 0 AS 0 and either UDS 0 or LDS 0 4 ns t5 A 20 0 SIZ 1 0 M R hold from AS 0 ns t6 CS hold from AS 0 ns t7 R W setup to DS 5 ns t8 R W hold from AS 0 ns t91 AS 0 and CS 0 to DSACK1 driven high 1 ns t10 AS high to DSACK1 high impedan...

Page 48: ... A 002 19 Issue Date 01 11 06 7 1 4 Generic MPU Interface Synchronous Timing Figure 7 4 Generic MPU Interface Synchronous Timing t2 t1 t2 t1 t1 t2 t1 t5 t10 t1 t4 t9 t2 t2 t1 t2 t3 t6 A 20 0 CS RD0 RD1 D 15 0 read WAIT t11 Hi Z Hi Z Hi Z Hi Z Valid WE0 WE1 M R TBCLK D 15 0 write Valid Hi Z Hi Z Valid t7 t8 BCLK ...

Page 49: ...R become valid whichever occurs later Table 7 4 Generic MPU Interface Synchronous Timing Symbol Parameter Min Max Units TBCLK Bus clock period 25 ns t1 A 20 0 M R CS RD0 RD1 WE0 WE1 hold time 1 ns t2 A 20 0 M R CS RD0 RD1 WE0 WE1 setup time 5 ns t3 RD0 RD1 WE0 WE1 high to A 20 0 M R invalid and CS high 0 ns t41 RD0 RD1 WE0 WE1 low and CS low to WAIT driven low 1 7 ns t5 BCLK to WAIT high 0 15 ns t...

Page 50: ...ecification X19A A 002 19 Issue Date 01 11 06 7 1 5 Generic MPU Interface Asynchronous Timing Figure 7 5 Generic MPU Interface Asynchronous Timing t1 t3 t9 t5 BCLK A 20 0 CS RD0 RD1 D 15 0 read WAIT t10 t2 t4 Valid Hi Z Hi Z Hi Z Hi Z Valid t8 WE0 WE1 M R TBCLK t7 t6 D 15 0 write Valid Hi Z Hi Z ...

Page 51: ...itive edge of BCLK after A 20 0 and M R become valid whichever occurs later Table 7 5 Generic MPU Interface Asynchronous Timing Symbol Parameter Min Max Units TBCLK Bus clock period 25 ns t1 RD0 RD1 WE0 WE1 low to CS low 4 ns t2 A 20 0 M R valid to RD0 RD1 WE0 WE1 low 0 ns t3 RD0 RD1 WE0 WE1 high to A 20 0 CS M R invalid and CS high 0 ns t41 CS low to WAIT driven low 1 7 ns t5 RD0 RD1 WE0 WE1 high...

Page 52: ...terface Timing 7 3 1 EDO DRAM Read Timing Figure 7 7 EDO DRAM Read Timing Table 7 6 Clock Input Requirements Symbol Parameter Min Typ Max Units TCLKI Input Clock Period CLKI 12 5 ns TPCLK Pixel Clock Period PCLK not shown 25 ns TMCLK Memory Clock Period MCLK not shown 25 ns tPWH Input Clock Pulse Width High CLKI 45 55 TCLKI tPWL Input Clock Pulse Width Low CLKI 45 55 TCLKI t PWL t PWH Clock Input ...

Page 53: ...up time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 CAS pulse width 0 45 t1 0 55 t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 1 t1 ns t10 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1 t1 1 ns t11 RAS to CAS delay time REG 22h bit 4 0 and bits 3 2 00 or 10 2 t1 2 2 t1 ...

Page 54: ...Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 3 2 EDO DRAM Write Timing Figure 7 8 EDO DRAM Write Timing t10 d1 t11 d2 d3 d4 t12 t13 t14 t15 t1 RAS CAS MA MD Write R C1 C2 C3 C4 t3 t4 t5 t6 t7 t8 t9 t2 WE Memory Clock ...

Page 55: ...REG 22h bits 3 2 00 or 10 0 45 t1 1 ns Row address hold time REG 22h bits 3 2 01 t1 1 ns t5 Column address setup time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 CAS pulse width 0 45 t1 0 55 t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 1 t1 ns t10 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge t...

Page 56: ...ign Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 3 3 EDO DRAM Read Write Timing Figure 7 9 EDO DRAM Read Write Timing RAS CAS MA MD Read t7 R C1 C2 C3 t4 t5 t6 t8 d2 t2 WE MD Write d1 d3 t9 t3 t10 t1 Memory Clock ...

Page 57: ... time REG 22h bits 3 2 10 1 45 t1 ns t4 Row address hold time REG 22h bits 3 2 00 or 10 0 45 t1 1 ns Row address hold time REG 22h bits 3 2 01 t1 1 ns t5 Column address setup time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1 t1 1 ns t8 RAS to CAS...

Page 58: ...harge time REG 22h bits 3 2 01 or 10 0 45 t1 ns t3 Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns t4 CAS precharge time REG 22h bits 3 2 00 2 t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t5 CAS setup time REG 22h bits 3 2 00 or 10 0 45 t1 2 ns CAS setup...

Page 59: ... time REG 22h bits 3 2 00 1 45 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 0 45 t1 ns t3 CAS precharge time REG 22h bits 3 2 00 2 t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t4 CAS setup time REG 22h bits 3 2 00 or 10 0 45 t1 2 ns CAS setup time REG 22h bits 3 2 01 1 t1 2 ns t5 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45...

Page 60: ...gn Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 3 6 FPM DRAM Read Timing Figure 7 12 FPM DRAM Read Timing d1 d2 RAS CAS MA MD Read t10 t12 t13 t15 R C1 C4 t3 t4 t6 t5 t7 t8 t11 t9 d3 d4 t14 t2 t1 C2 C3 Memory Clock ...

Page 61: ...ns t7 CAS pulse width 0 45 t1 0 55 t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 0 45 t1 ns t10 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1 t1 1 ns t11 RAS to CAS delay time REG 22h bit 4 1 and bits 3 2 00 or 10 1 45 t1 2 1 55 t1 ns RAS to CAS delay time REG 22h bit 4 0 and bits ...

Page 62: ...Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 3 7 FPM DRAM Write Timing Figure 7 13 FPM DRAM Write Timing RAS CAS MA t10 R C1 t3 t4 t6 t5 t7 t8 t11 t9 t2 t1 C3 MD Write d1 d2 d3 d4 WE t13 t14 t15 t12 C4 C2 Memory Clock ...

Page 63: ... time REG 22h bits 3 2 01 0 45 t1 1 ns t5 Column address set up time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 CAS pulse width 0 45 t1 0 55 t1 1 ns t8 CAS precharge time 0 45 t1 1 0 55 t1 ns t9 RAS hold time 0 45 t1 ns t10 RAS precharge time REG 22h bits 3 2 00 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1 t1 1 ns t11 RAS to C...

Page 64: ...ign Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 7 3 8 FPM DRAM Read Write Timing Figure 7 14 FPM DRAM Read Write Timing R C2 C3 t7 C1 t3 t4 t6 t5 t8 t2 t1 t9 t10 RAS CAS MA MD Read d2 WE MD Write d3 Memory Clock d1 ...

Page 65: ...its 3 2 10 1 t1 ns t4 Row address hold time REG 22h bits 3 2 00 or 10 t1 1 ns Row address hold time REG 22h bits 3 2 01 0 45 t1 1 ns t5 Column address set up time 0 45 t1 1 ns t6 Column address hold time 0 45 t1 1 ns t7 RAS precharge time REG 22h bits 3 2 0 2 t1 1 ns RAS precharge time REG 22h bits 3 2 01 1 45 t1 1 ns RAS precharge time REG 22h bits 3 2 10 1 t1 1 ns t8 RAS to CAS delay time REG 22...

Page 66: ... 22h bits 3 2 00 2 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t3 Random read or write cycle time REG 22h bits 6 5 00 5 t1 ns Random read or write cycle time REG 22h bits 6 5 01 4 t1 ns Random read or write cycle time REG 22h bits 6 5 10 3 t1 ns t4 CAS precharge time REG 22h bits 3 2 00 2 t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t5 CAS setup time CAS before ...

Page 67: ...ts t1 Memory clock 40 ns t2 RAS to CAS precharge time REG 22h bits 3 2 00 2 t1 ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t3 CAS precharge time REG 22h bits 3 2 00 2 t1 ns CAS precharge time REG 22h bits 3 2 01 or 10 1 t1 ns t4 CAS setup time CAS before RAS refresh 0 45 t1 2 ns t5 RAS precharge time REG 22h bits 3 2 00 2 45 t1 1 ns RAS precharge time REG 22h bits 3 2 01 or 10 1...

Page 68: ...he period of FPFRAME and TPCLK is the period of the pixel clock Table 7 17 LCD Panel Power On Reset Timing Symbol Parameter Min Typ Max Units TRESET RESET pulse time 100 us t1 LCD Enable bit high to FPLINE FPSHIFT FPDAT 15 0 DRDY active TFPFRAME 6TPCLK ns t2 FPLINE FPSHIFT FPDAT 15 0 DRDY active to LCDPWR on and FPFRAME active 128 Frames RESET LCD ENABLE LCDPWR FPFRAME FPLINE FPSHIFT FPDAT 15 0 DR...

Page 69: ...tive to CLKI inactive 128 Frames t2 SUSPEND active to FPFRAME LCDPWR inactive 0 1 Frames t3 First CLKI after SUSPEND inactive to FPFRAME LCDPWR active 1 Frames t4 LCDPWR inactive to FPLINE FPSHIFT FPDAT 15 0 DRDY active 128 Frames t5 First CLKI after SUSPEND inactive to FPLINE FPSHIFT FPDAT 15 0 DRDY active 0 Frames t6 LCDPWR inactive to Memory Access not allowed 8 MCLK t7 First CLKI after SUSPEND...

Page 70: ...bits 1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts VDP FPLINE FPSHIFT LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 FPFRAME LINE1 LINE2 FPLINE MOD 1 2 1 6 1 318 1 3 1 7 1 319 1 4 1 8 1 320 1 1 1 5 1 317 MOD VNDP HDP HNDP Diagram drawn with 2 FPLINE vertical blank pe...

Page 71: ...eter Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t8 FPSHIFT period 4 Ts t9 FPSHIFT falling edge to FPLINE fallin...

Page 72: ...al Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts HNDP VDP FPLINE FPSHIFT LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE MOD 1 2 1 10 1 634 1 3 1 11 1 635 1 4 1 12 1 636 1 5 1 13 1 637 1 6 1 14 1 638 1 7 1 15 1 639 1 8 1 16 1 640 1 1 1 9 1 633 MOD VNDP HDP Diagram drawn with 2 ...

Page 73: ...p Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t8 FPSHIFT period 8 Ts t9 FPSHIFT falling edge to FPLINE falling edge note...

Page 74: ...bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts VDP FPLINE UD 3 0 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE MOD UD2 UD1 UD0 UD3 MOD VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 B319 1 R320 1 G320 1 B320 HDP HNDP Diagram drawn w...

Page 75: ...Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t8 FPSHIFT period 1 Ts t9 FPSHIFT falling edge to FPLINE falling edge note...

Page 76: ...DP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts VDP FPLINE FPSHIFT2 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 HDP VNDP 1 R1 1 B1 1 G2 1 R3 1 B3 1 G4 1 R5 1 B5 1 G1 1 R2 1 B2 1 G3 1 R4 1 B4 1 G5 1 R6 1 G6 1 R7 1 B7 1 G8 1 R9 1 B9 1 G10 1 R11 1 B6 1 G7 1 R8 1 B8 1 G9 1 R10 1 B10 1 G11 1 R636 1 B636 1 G637 1 R638 1 B638 1 G639 1 R640 1 ...

Page 77: ...dge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5a FPSHIFT2 falling edge to FPLINE rising edge note 4 t5b FPSHIFT falling edge to FPLINE rising edge note 5 t6 FPLINE falling edge to FPSHIFT2 rising FPSHIFT falling edge t14 2 Ts t7 FPSHIFT2 FPSHIFT period 4 Ts t8a FPSHIFT falling edge to FPLINE falling edge note 6 t8b FPSHIFT2 fall...

Page 78: ... 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts VDP FPLINE UD 3 0 LD 3 0 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE MOD UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 MOD VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 R5 1 G5 1 B5 1 R6 1 G6 1 B6 1 R7 1 G7 1 B7 1 R8 1 G8 1 B8 1 G638 1 B638 1 ...

Page 79: ...Min Typ Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period...

Page 80: ... 8Ts VDP FPLINE FPSHIFT UD 7 0 LD 7 0 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 FPFRAME LINE1 LINE2 FPLINE MOD UD6 UD5 UD4 UD3 UD2 UD1 UD0 UD7 MOD VNDP HDP 1 R1 1 G6 1 G635 1 B1 1 R7 1 G636 1 G2 1 B7 1 R637 1 R3 1 G8 1 B637 1 B3 1 R9 1 G638 1 G4 1 B9 1 R639 1 R5 1 G10 1 B639 1 G1 1 B6 1 R636 1 R2 1 G7 1 B636 1 B2 1 R8 1 G637 1 G3 1 B8 1 R638 1 R4 1 G9 1 B638 1 B4 1 R10 1 G639 1 G5 1 B10 1 R640 1 R6 ...

Page 81: ...x Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t...

Page 82: ...its 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG 05h bits 4 0 1 8Ts VDP FPLINE FPSHIFT UD 3 0 LD 3 0 FPFRAME FPLINE MOD UD2 1 2 1 6 1 638 UD1 1 3 1 7 1 639 UD0 1 4 1 8 1 640 LD3 241 1 241 5 241 637 LD2 241 638 LD1 241 639 LD0 241 640 UD3 1 1 1 5 1 637 HDP MOD 241 2 241 6 241 3 241 7 241 4 241 8 VNDP HNDP Diagram drawn with 2 FPLINE vertical blan...

Page 83: ...Max Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts...

Page 84: ...d REG 05h bits 4 0 1 8Ts VDP FPLINE UD 3 0 LD 3 0 FPFRAME FPLINE MOD UD2 UD1 UD0 LD3 LD2 LD1 LD0 UD3 MOD VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 R5 1 G5 1 B5 1 R6 1 G6 1 B6 1 R7 1 G7 1 R8 1 G8 1 B8 1 B639 1 R640 1 G640 1 B640 241 B639 241 R640 241 G640 241 B640 241 R1 241 G1 241 B1 241 R2 241 G2 241 B2 241 R3 241 G3 241 B3 241 R4 241 G4 241 B4 241 R5 241 G5 241 B5 241 R6...

Page 85: ...1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 1 Ts t9 FPSHIFT period 1 Ts t10 FPSHIF...

Page 86: ... 0 1 8Ts 9 VDP FPLINE FPSHIFT UD 7 0 LD 7 0 FPFRAME FPLINE MOD UD6 LD6 UD5 LD5 UD4 LD4 UD3 LD3 UD2 LD2 UD1 LD1 UD0 LD0 UD7 LD7 MOD VNDP Diagram drawn with 2 FPLINE vertical blank period 1 R1 241 R1 1 B3 241 B3 1 G638 241 G638 1 B1 241 B1 1 G4 241 G4 1 R639 241 R639 1 R2 241 R2 1 B4 241 B4 1 G639 241 G63 1 G2 241 G2 1 R5 241 R5 1 B639 241 B639 1 B2 241 B2 1 G5 241 G5 1 R640 241 R640 1 R3 241 R3 1 B...

Page 87: ... Units t1 FPFRAME setup to FPLINE falling edge note 2 t2 FPFRAME hold from FPLINE falling edge 9 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD transition to FPLINE falling edge 33 note 4 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 5 t7 FPSHIFT falling edge to FPLINE falling edge note 6 t8 FPLINE falling edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period 2 Ts t10 F...

Page 88: ...its 1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 REG 05h bits 4 0 1 8Ts FPFRAME FPLINE LINE1 LINE480 1 1 1 1 1 1 1 2 1 2 1 2 1 640 1 640 1 640 FPLINE FPSHIFT DRDY R 5 1 G 5 0 B 5 1 R 5 1 G 5 0 B 5 1 VDP DRDY Note DRDY is used to indicate the first pixel Example Timing f...

Page 89: ...ware Functional Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 Figure 7 38 TFT A C Timing t12 t7 FPLINE t8 t6 FPFRAME DRDY FPSHIFT 640 t9 FPLINE 2 1 639 R 5 1 t13 t2 t3 t16 t4 t5 t14 t15 t1 t11 t10 G 5 0 B 5 1 Note DRDY is used to indicate the first pixel t17 ...

Page 90: ...8 REG 06h bits 4 0 1 8 2 Table 7 28 TFT A C Timing Symbol Parameter Min Typ Max Units t1 FPSHIFT period 1 Ts note 1 t2 FPSHIFT pulse width high 0 45 Ts t3 FPSHIFT pulse width low 0 45 Ts t4 data setup to FPSHIFT falling edge 0 45 Ts t5 data hold from FPSHIFT falling edge 0 45 Ts t6 FPLINE cycle time note 2 t7 FPLINE pulse width low note 3 t8 FPFRAME cycle time note 4 t9 FPFRAME pulse width low not...

Page 91: ...VDP Vertical Display Period REG 09h bits 1 0 REG 08h bits 7 0 1 VNDP Vertical Non Display Period REG 0Ah bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 REG 05h bits 4 0 1 8Ts VRTC HRTC LINE1 LINE480 1 1 1 2 1 640 HRTC DACCLK BLANK DACP 7 0 DACD 7 0 VDP HDP VNDP HNDP1 BLANK Example Timing for 640x480 CRT HNDP2 LINE480 ...

Page 92: ...ment Vancouver Design Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 Figure 7 40 CRT A C Timing t12 t7 HRTC t8 t6 VRTC BLANK DACCLK 640 t9 HRTC 2 1 639 t13 t2 t3 t16 t4 t5 t14 t15 t1 t11 t10 DACD 7 0 ...

Page 93: ...EG 06h bits 4 0 1 8 2 Ts Table 7 29 CRT A C Timing Symbol Parameter Min Typ Max Units t1 DACCLK period 1 Ts note 1 t2 DACCLK pulse width high 0 45 Ts t3 DACCLK pulse width low 0 45 Ts t4 data setup to DACCLK rising edge 0 45 Ts t5 data hold from DACCLK rising edge 0 45 Ts t6 HRTC cycle time note 2 t7 HRTC pulse width shown active low note 3 t8 VRTC cycle time note 4 t9 VRTC pulse width shown activ...

Page 94: ... Parameter Min Typ Max Units TBCLK Bus clock period 30 ns t1 AB 20 0 CS M R delay to DACRS 1 0 10 ns t2 DACRS 1 0 hold from AB 20 0 CS M R negated 10 ns t3 Valid RD command to DACRS 1 0 delay 8 33 ns t4 DACRD hold from valid RD command negated 3 14 ns t5 Valid WR command to DACWR delay 2 TBCLK ns t6 DACWR pulse width low 2 45 TBCLK 2 55 TBCLK ns AB 20 0 Valid RD Command t1 DACRS 1 0 t5 Write t3 t4...

Page 95: ...ld be written 0 when programming unless otherwise noted 8 2 1 Revision Code Register bits 7 2 Product Code Bits 5 0 This is a read only register that indicates the product code of the chip The product code is 000001 bits 1 0 Revision Code Bits 1 0 This is a read only register that indicates the revision code of the chip The revision code is 00 Table 8 1 S1D13504 Addressing CS M R Access 0 0 Regist...

Page 96: ...cted This bit should be changed only when there are no read write DRAM cycles This condition occurs when both the Display FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 For programming information see S1D13504 Programming Notes and Examples document number X19A G 002 xx Memory Configuration Register REG 01h RW n a Refresh Rate Bit 2 Refresh Rate Bit 1 Refres...

Page 97: ...idle during vertical non display periods or while in suspend mode For programming information see S1D13504 Programming Notes and Examples document number X19A G 002 xx bit 0 TFT Passive LCD Panel Select When this bit 1 TFT panel is selected When this bit 0 passive LCD panel is selected bits 5 0 MOD Rate Bits 5 0 For a non zero value these bits specify the number of FPLINE between toggles of the MO...

Page 98: ...register must be programmed such that REG 05h 3 and REG 05h 1 REG 06h 1 REG 07h bits 3 0 1 bits 4 0 HRTC FPLINE Start Position Bits 4 0 For CRTs and TFTs these bits specify the delay from the start of the horizontal non display period to the leading edge of the HRTC pulse and FPLINE pulse respectively Contents of this Register HRTC FPLINE Start Position 8 1 The maximum HRTC start delay is 256 pixe...

Page 99: ...bits 3 0 1 REG 08h bits 7 0 Vertical Display Height Bits 9 0 REG 09h bits 1 0 These bits specify the LCD panel and or the CRT vertical display height in 1 line resolution For a dual LCD panel only configuration this register should be programmed to half the panel size Vertical display height in number of lines ContentsOfThisRegister 1 The maximum vertical display height is 1024 lines HRTC FPLINE P...

Page 100: ...ion Bits 5 0 For CRTs and TFTs these bits specify the delay in lines from the start of the vertical non display period to the leading edge of the VRTC pulse and FPFRAME pulse respectively For passive LCDs FPFRAME is automatically created and these bits have no effect VRTC FPFRAME start position lines VRTC FPFRAME Start Position Bits 5 0 1 The maximum VRTC start delay is 64 lines Note This register...

Page 101: ...sive LCD bits 2 0 VRTC FPFRAME Pulse Width Bits 2 0 For CRTs and TFTs these bits specify the pulse width of VRTC and FPFRAME respectively For passive LCDs FPFRAME is automatically created and these bits have no effect VRTC FPFRAME pulse width lines VRTC FPFRAME Pulse Width Bits 2 0 1 The maximum VRTC pulse width is 8 lines Note This register must be programmed such that REG 0Ah bits 5 0 1 REG 0Bh ...

Page 102: ...r to be washed out due to the 1 525 duty cycle of the CRT Line Doubling each line is sent to the CRT twice giving a 640x480 image which has a long aspect ratio The image on the LCD has each line sent twice but only one FPLINE This gives a duty cycle of 2 525 which is very close to the LCD only mode duty cycle of 1 242 so the image on the LCD will have almost the same contrast as that of a single L...

Page 103: ...ported on CRT See Figure 10 2 15 16 Bit Per Pixel Format Memory Organization on page 116 for a description of passive panel support bit 1 CRT Enable This bit enables the CRT control signals Note REG 02h bit 1 must 0 when in CRT only mode bit 0 LCD Enable This bit enables the LCD control signals Programming this bit from a 0 to a 1 starts the LCD power on sequence Programming this bit from a 1 to a...

Page 104: ...this register must be set greater than the vertical display height REG 08h and REG 09h e g set to 3FFh For split screen on a single panel Split screen 1 vertical size in number of lines ContentsOfThisRegister 1 For split screen on a dual panel Split screen 1 vertical size in number of lines ContentsOfThisRegister 1 if ContentsOfThisRegister 00EFh or Split screen 1 vertical size in number of lines ...

Page 105: ...on page 115 for details Screen 1 Display Start Address Register 0 REG 10h RW Start Address Bit 7 Start Address Bit 6 Start Address Bit 5 Start Address Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0 Screen 1 Display Start Address Register 1 REG 11h RW Start Address Bit 15 Start Address Bit 14 Start Address Bit 13 Start Address Bit 12 Start Address Bit 11 Start...

Page 106: ...th horizontal panning can be achieved by a combination of this register and the Display Start Address register See Section 10 Display Configuration on page 115 and S1D13504 Programming Notes and Examples document number X19A G 002 xx Section 4 for details bits 7 4 Screen 2 Pixel Panning Bits 3 0 Pixel panning bits for screen 2 bits 3 0 Screen 1 Pixel Panning Bits 3 0 Pixel panning bits for screen ...

Page 107: ...ESET When this bit 0 the LCDPWR output is controlled by the panel on off sequencing logic See Table 5 8 Summary of Power On Reset Options on page 30 bits 2 1 Suspend Refresh Select Bits 1 0 These bits specify the type of DRAM refresh to use in Suspend mode Note These bits should not be changed when suspend mode is enabled bit 0 Software Suspend Mode Enable When this bit 1 software suspend mode is ...

Page 108: ...t results in reduced contrast on the LCD panel This mode is not normally used except in special circumstances such as simultaneous display on a CRT and dual panel LCD See Section 11 2 on page 119 for details Note The Half Frame Buffer should be disabled only when idle The Half Frame Buffer is idle during vertical non display periods i e when REG 0Ah bit 7 1 or while in suspend mode For programming...

Page 109: ...ing edge of RESET to enable GPIO4 otherwise the DACRD pin is controlled automatically and this bit will have no effect on hardware bit 3 GPIO3 Pin IO Configuration When this bit 1 GPIO3 is configured as an output When this bit 0 default GPIO3 is config ured as an input Note the MD 7 6 pins must be properly configured at the rising edge of RESET to enable GPIO3 otherwise the MA9 pin is controlled a...

Page 110: ...ect on hardware bit 1 GPIO9 Pin IO Configuration When this bit 1 GPIO9 is configured as an output When this bit 0 default GPIO9 is config ured as an input Note GPIO9 and GPIO8 must always be set to the same function both to input or both to output The MD8 pin must be high at the rising edge of RESET to enable GPIO9 otherwise the DACRS1 pin is controlled automatically and this bit will have no effe...

Page 111: ...ing edge of RESET to enable GPIO4 other wise the DACRD pin is controlled automatically and this bit will have no effect on hardware bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output a 1 in this bit drives GPIO3 to high and a 0 in this bit drives GPIO3 to low When GPIO3 is configured as an input a read from this bit returns the status of GPIO3 Note the MD 7 6 pins must be properly con...

Page 112: ...atically and this bit will have no effect on hardware bit 2 GPIO10 Pin IO Status When GPIO10 is configured as an output a 1 in this bit drives GPIO10 to high and a 0 in this bit drives GPIO10 to low When GPIO10 is configured as an input a read from this bit returns the status of GPIO10 Note the MD8 pin must be high at the rising edge of RESET to enable GPIO10 otherwise the HRTC pin is controlled a...

Page 113: ...s 1 MCLK delay for the read write transi tion This bit may be programmed to 1 when the MCLK frequency is less than 30MHz bits 6 5 RC Timing Value NRC Bits 1 0 These bits select the DRAM random cycle timing parameter tRC These bits specify the number NRC of MCLK periods TM used to create tRC NRC should be chosen to meet tRC as well as tRAS the RAS pulse width Use the following two formulae to calcu...

Page 114: ... time tASC The resulting tRC is related to NRCD as follows tRC NRCD TM if EDO and NRP 1 or 2 tRC 1 5 TM if EDO and NRP 1 5 tRC NRCD 0 5 TM if FPM and NRP 1 or 2 tRC NRCD TM if FPM and NRP 1 5 bits 3 2 RAS Precharge Timing NRP Bits 1 0 Minimum Memory Timing for RAS precharge These bits select the DRAM RAS Precharge timing parameter tRP These bits specify the number NRP of MCLK periods TM used to cr...

Page 115: ...04 to be dedicated to service CPU to memory accesses When this bit 0 the display FIFO is enabled bits 4 0 Display FIFO Threshold Bits 4 0 These bits should be set to a value of 10h upon initialization as this provides the best overall perfor mance for all display modes Table 8 14 Optimal NRC NRP and NRCD Values at Maximum MCLK Frequency DRAM Type DRAM Speed ns TM ns NRC MCLK NRP MCLK NRCD MCLK EDO...

Page 116: ...B LUT A read write access to the LUT data will increment the LUT address by 1 bits 3 0 LUT Address Bits 3 0 These 4 bits provide a pointer into the 16 position Look Up Table currently selected for CPU read write access The Look Up Table configuration e g 1 2 4 banks does not affect the read write access from the CPU as all 16 positions can be accessed sequentially bits 3 0 LUT Data Bits 3 0 These ...

Page 117: ...le Endian architecture the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register 28h 2Ah 2Ch and 2Eh In a Big Endian architecture the RAMDAC should be connected to the high byte of the CPU data bus and the following registers are accessed at the higher address given for each register 29h 2Bh 2Dh and 2Fh ...

Page 118: ...tle Endian system or data bus bits 15 8 in a Big Endian system bits 7 0 RAMDAC Palette Data Bits 7 0 A CPU read or write to this register will generate a DACRD or DACWR pulse and DACRS1 0 and DACRS0 1 to the external RAMDAC for a palette data register access The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits 7 0 in a Little...

Page 119: ... 512K byte display buffer is replicated in the 2M byte address space as shown below Figure 9 1 Display Buffer Addressing The display buffer will contain an image buffer and may also contain a half frame buffer Table 9 1 S1D13504 Addressing CS M R Access 0 0 Register access REG 00h is addressed when AB 5 0 0 REG 01h is addressed when AB 5 0 1 REG n is addressed when AB 5 0 n 0 1 Memory access the 2...

Page 120: ...n the relationship between the image buffer and the display 9 2 Half Frame Buffer In dual panel mode with the half frame buffer enabled the top of the display buffer is allocated to the half frame buffer The size of the half frame buffer is a function of the panel resolution and whether the panel is color or monochrome Half Frame Buffer Size in bytes panel width x panel length factor 16 where fact...

Page 121: ...t Address Display Buffer A4 B4 A5 B5 A6 B6 A7 B7 bit 7 bit 0 bit 7 bit 0 4 bpp A0 B0 C0 D0 A1 B1 C1 D1 Host Address Display Buffer A2 B2 C2 D2 A3 B3 C3 D3 bit 7 bit 0 A4 B4 C4 D4 A5 B5 C5 D5 Host Address Display Buffer bit 7 bit 0 8 bpp 3 3 2 RGB R0 2 R0 1 R0 0 G0 2 G0 1 G0 0 B0 1 B0 0 R1 2 R1 1 R1 0 G1 2 G1 1 G1 0 B1 1 B1 0 R2 2 R2 1 R2 0 G2 2 G2 1 G2 0 B2 1 B2 0 Byte 0 Byte 0 Byte 1 Byte 0 Byte ...

Page 122: ...Buffer bit 7 bit 0 Panel Display P0P1P2 P3P4P5P6 P7 R0 3 R0 2 R0 1 R0 0 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 16 bpp R0 4 Host Address Display Buffer bit 7 bit 0 R0 3 R0 2 R0 1 R0 0 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 R1 4 R1 3 R1 2 R1 1 R1 0 G1 5 G1 4 G1 3 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 5 6 5 RGB 5 5 5 RGB R1 4 R1 3 R...

Page 123: ...10h defines the starting word of the screen 1 REG 15h REG 14h REG 13h defines the starting word of the screen 2 REG 18h bits 3 0 define the starting pixel within the starting word for screen 1 REG 18h bits 7 4 define the starting pixel within the starting word for screen 2 REG 0Fh REG 0Eh define the last line of screen 1 the remainder of the display is taken up by screen 2 Figure 10 3 Image Manipu...

Page 124: ...ame Buffer Enabled Simultaneous CRT Dual Color Panel with Half Frame Buffer Enable 5 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Table 11 2 Maximum PCLK Frequency with FPM DRAM Display type NRC Maximum PCLK allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Single Panel CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Simultaneous...

Page 125: ...RAM Type1 Speed Grade Display Resolution Color Depth bpp Maximum Pixel Clock MHz Minimum Panel HNDP Ts Maximum Frame Rate Hz Panel4 CRT 50ns EDO DRAM MClk 40MHz NRC 4 NRP 1 5 NRCD 2 Single Panel CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 Simultaneous CRT Single Panel Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 800x6002 1 2 4 8 40 32 80 60 1...

Page 126: ...16 56 98 78 640x240 1 2 4 8 32 203 16 56 200 480x320 1 2 4 8 32 200 16 56 196 320x240 1 2 4 8 32 388 16 56 380 Dual Color with Half Frame Buffer Enabled Dual Mono with Half Frame Buffer Enabled 800x6002 3 1 2 4 8 16 5 32 66 16 11 32 43 640x480 1 2 4 8 16 5 32 103 16 11 32 68 60ns FPM DRAM MClk 25MHz NRC 4 NRP 1 5 NRCD 2 Single Panel CRT Dual Mono Color Panel with Half Frame Buffer Disabled 5 Simul...

Page 127: ...de Look Up Table Architecture Table 12 1 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table RED GREEN BLUE Black White 1 bank of 2 entries 4 level gray 4 banks of 4 entries 16 level gray 1 bank of 16 entries 2 color 1 bank of 2 entries 1 bank of 2 entries 1 bank of 2 entries 4 color 4 banks of 4 entries 4 banks of 4 entries 4 banks of 4 entries 16 color 1 bank of 16 entries 1 bank ...

Page 128: ...d to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations Green Look Up Table 0 1 2 3 2 bit pixel data 4 5 6 7 8 9 A B C D E F Bank 0 Bank 1 Bank 2 Bank 3 Bank Select bits 1 0 REG 27h bits 1 0 4 bit display data output Bank Select Logic Entry Select Logic 00 01 10 11 00 01 10 11 Selected Bank 4 bit pixel da...

Page 129: ...2 2 Color Display Modes 1 Bit Per Pixel Color Mode Figure 12 4 1 Bit Per Pixel 2 Level Color Look Up Table Architecture Red Look Up Table 0 1 1 bit pixel data 4 bit Red data output Entry Select Logic 0 1 Green Look Up Table 0 1 4 bit Green data output Entry Select Logic 0 1 Blue Look Up Table 0 1 4 bit Blue data output Entry Select Logic 0 1 ...

Page 130: ...ts 1 0 REG 27h bits 5 4 4 bit Red data output Bank Select Logic Entry Select Logic 00 01 10 11 00 01 10 11 Selected Bank Green Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Bank 0 Bank 1 Bank 2 Bank 3 Bank Select bits 1 0 REG 27h bits 1 0 4 bit Green data output Bank Select Logic Entry Select Logic 00 01 10 11 00 01 10 11 Selected Bank Blue Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Bank 0 Bank...

Page 131: ...ok Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Select Logic 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1001 1100 1101 1110 1111 4 bit Green data output Green Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Select Logic 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1001 1100 1101 1110 1111 4 bit Blue data output Blue Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Se...

Page 132: ...k Select bit REG 27h bit 4 4 bit Red data output Bank Select Logic Entry Select Logic 0 1 000 001 010 011 Selected Bank 100 101 110 111 Green Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Bank 0 Bank 1 Bank Select bit REG 27h bit 0 4 bit Green data output Bank Select Logic Entry Select Logic 0 1 000 001 010 011 Selected Bank 100 101 110 111 Blue Look Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F Bank 0...

Page 133: ... to Off state CRT outputs are disabled If suspend mode CBR refresh is selected all internal modules and clocks except the Memory I F are shut down If suspend mode self refresh or no refresh is selected all internal modules and clocks are shut down 13 2 Software Suspend Register read write allowed except for RAMDAC registers Memory read write disallowed LCD outputs are forced low see Note 1 of Sect...

Page 134: ...D DACRS0 DACRS1 are active but DACCLK is disabled 4 Active for non DAC register access only Table 13 1 Power Save Mode Function Summary Function Power Save Mode PSM Normal Active Software Suspend Hardware Suspend Display Active Yes No No Register Access Possible Yes Yes 1 No Memory Access Possible Yes No No Host Bus Interface Running Yes Yes No Memory Interface Running Yes No 2 No 2 Table 13 2 Pin...

Page 135: ... Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 14 Mechanical Data 14 1 QFP15 128 S1D13504F00A Figure 14 1 Mechanical Drawing QFP15 128 QFP15 128 pin 1 32 96 65 64 33 97 128 Index 0 10 14 0 0 1 14 0 0 1 16 0 0 4 16 0 0 4 0 4 0 16 0 1 1 4 0 1 0 125 0 1 1 0 0 5 0 2 Unit mm 0 1 ...

Page 136: ...e Functional Specification X19A A 002 19 Issue Date 01 11 06 14 2 TQFP15 128 S1D13504F01A Figure 14 2 Mechanical Drawing TQFP15 128 TQFP15 128 pin Unit mm 65 96 33 64 INDEX 32 1 128 97 14 0 1 16 0 4 14 0 1 16 0 4 0 16 0 4 0 05 0 03 1 0 1 0 1 1 2 max 1 0 5 0 2 0 10 0 125 0 05 0 025 ...

Page 137: ...onal Specification S1D13504 Issue Date 01 11 06 X19A A 002 19 14 3 QFP20 144 S1D13504F02A Figure 14 3 Mechanical Drawing QFP20 144 QFP20 144 pin Unit mm 20 0 1 22 0 4 73 108 20 0 1 22 0 4 37 72 INDEX 0 2 36 1 144 109 1 4 0 1 0 1 1 7 max 1 0 5 0 2 0 10 0 125 0 5 0 1 0 05 0 05 0 025 ...

Page 138: ...Wind River UGL v1 2 Display Drivers X19A E 003 xx S1D13504 Programming Notes And Examples X19A G 002 xx S5U13504B00C Evaluation Board User Manual X19A G 004 xx Interfacing to the Philips MIPS PR31500 PR31700 Microprocessor X19A G 005 xx S1D13504 Power Consumption X19A G 006 xx Interfacing to the NEC VR4102 Microprocessors X19A G 007 xx Interfacing to the ODO Display Card Interface X19A G 008 xx In...

Page 139: ... Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Mun...

Page 140: ...Page 134 Epson Research and Development Vancouver Design Center S1D13504 Hardware Functional Specification X19A A 002 19 Issue Date 01 11 06 THIS PAGE LEFT BLANK ...

Page 141: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 142: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 143: ...y Buffer Organization 12 3 2 1 Memory Organization for One Bit per pixel 2 Colors Gray Shades 12 3 2 2 Memory Organization for Two Bit per pixel 4 Colors Gray Shades 12 3 2 3 Memory Organization for Four Bit per pixel 16 Colors Gray Shades 13 3 2 4 Memory Organization for Eight Bit per pixel 256 Colors 13 3 2 5 Memory Organization for 15 Bit per pixel 32768 Colors 14 3 2 6 Memory Organization for ...

Page 144: ...troduction 33 6 1 1 CRT Only 33 6 1 2 Simultaneous Display 34 7 Identifying the S1D13504 38 8 Hardware Abstraction Layer HAL 39 8 1 Introduction 39 8 2 API for 13504HAL 39 8 2 1 Initialization 39 8 2 2 Screen Manipulation 41 8 2 3 Color Manipulation 47 8 2 4 Drawing 50 8 2 5 Register Manipulation 52 8 2 6 Miscellaneous 52 9 Sample Code 54 9 1 Introduction 54 9 1 1 Sample code using 13504HAL API 54...

Page 145: ...1 bpp Color Mode 18 Table 3 9 Recommended LUT Values for 2 bpp Color Mode 18 Table 3 10 Recommended LUT Values to Simulate VGA Default 16 Color Palette 19 Table 3 11 Recommended LUT Values For 8 bpp Color Mode 19 Table 3 12 Examples of 256 Pixel Colors Using Linear LUT 20 Table 3 13 Recommended LUT Values for 1 bpp Gray Shades 20 Table 3 14 Recommended LUT Values for 2 bpp Gray Shades 21 Table 3 1...

Page 146: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Programming Notes and Examples X19A G 002 07 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 147: ... guide presents the basic concepts of the LCD CRT controller and provides methods to directly program the registers It explains some of the advanced techniques used and the special features of the S1D13504 The guide also introduces the hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13504 Most S1D1350x S1D1370x and S1D1380x products support the HAL allowing O...

Page 148: ... should be programmed only during initialization and never changed after that However it still must be programmed BEFORE the internal blocks start to R W the memory see Register Initialization in Section 2 1 5 2 1 2 REG 22 bits 7 2 Performance Enhancement Register 0 This bit must not be changed during a DRAM R W access Configuring this bit during a DRAM Refresh will not cause any problems Note Thi...

Page 149: ... resolution 0 HFB enabled default power on state 2 1 5 REG 23 Display FIFO This register can be asynchronously enabled disabled Note The Display FIFO starts to access DRAM after RESET 2 2 Register Initialization 2 2 1 Initialization Sequence To initialize the S1D13504 after POWER ON or a HARDWARE RESET do the following 1 Enable the host interface REG 1Bh bit 7 0 2 Disable the display FIFO REG 23h ...

Page 150: ...e not programmed For code examples see Section 9 Sample Code on page 54 Table 2 1 Initializing the S1D13504 Registers Operation Description REG 1Bh 0x00 Enable Host Interface REG 23h 0x80 Disable the Display FIFO REG 01h 0x30 Set Memory Type REG 22h 0x24 Set Performance Register REG 02h 0x26 Set Dual Single Panel REG 03h 0x00 MOD Rate REG 04h 0x4F Horizontal Display Width REG 05h 0x1F Horizontal N...

Page 151: ... REG 04 0 Setting the horizontal resolution 0 will shut off any Half Frame Buffer DRAM accesses within 1024 PCLK s or less 1024 PCLK s is the worst case 3 Wait for VNDP 1 0 1 transitions REG 0A bit 7 Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle 4 Disable the Half Frame Buffer REG 1B bit 0 1 5 Re program the horizontal resolution to your original value REG 20h 0x00 RE...

Page 152: ...ray by indexing into positions 0 and 1 of the Green Look Up Table LUT and two levels of color by indexing into positions 0 and 1 of the Red Green Blue LUTs 3 2 2 Memory Organization for Two Bit per pixel 4 Colors Gray Shades Four pixels are grouped into one byte of display buffer as shown below Two bit per pixel provides four shades of gray by indexing into positions 0 through 3 of the Green LUT a...

Page 153: ...three parts three bits for red three bits for green and two bits for blue The red bits represent an index into the red LUT the green bits represent an index into the green LUT and the blue bits represent an index into the blue LUT Although eight bit per pixel only makes sense for a color panel this memory model can be set on a monochrome panel however only eight shades of gray will be visible Tabl...

Page 154: ...to three parts five bits for red six bits for green and five bits for blue The output bypasses the LUT and goes directly into the Frame Rate Modulator Although 16 bit per pixel only make sense for a color panel this memory model can be set on a monochrome panel however only 16 shades of gray will be visible Table 3 5 Pixel Storage for 15 bpp 32768 Colors in Two Bytes of Display Buffer Bit 15 Bit 1...

Page 155: ...e writes reads it will increment to Green then Blue of the same index it will then increment the index and start at the Red LUT again Auto increment algorithm 1 Set RGB Index to 0 for Auto increment set LUT address to 0 i e REG 24h 00h 2 While count or to 16 3 write data byte to REG 26h R G or B Index select algorithm 1 Set RGB Index to R 01b G 10b or B 11b set LUT address to 0 e g REG 24h 10h 2 W...

Page 156: ...ypass the LUT or have only Bank 0 starting at Index 00h In 2 bpp mode the 16 entry LUTs are logically split into 4 groups of 4 entries for each of R G B Bank 0 Indexes 00 03h Bank 1 Indexes 04 07h Bank 2 Indexes 08 0Bh Bank 3 Indexes 0C 0Fh In 8 bpp mode the 16 entry LUTs are logically split into 2 groups of 8 entries for both Red and Green as follows Bank 0 Indexes 00 07h Bank 1 Indexes 08 0Fh Fo...

Page 157: ...ght red output Table 3 7 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table Effective Grays Colors on an Passive Panel RED GREEN BLUE 1 bpp gray 1 bank of 2 2 gray shades 2 bpp gray 4 banks of 4 4 gray shades 4 bpp gray 1 bank of 16 16 gray shades 8 bpp gray 2 banks of 8 8 gray shades 15 bpp gray 16 gray shades 16 bpp gray 16 gray shades 1 bpp color 1 bank of 2 1 bank of 2 1 bank o...

Page 158: ...es are divided into four separate 4 entry banks per color The following table demonstrates recommended LUT data values which produce Bank 0 low intensity Bank 1 high intensity Bank 2 inverted low intensity Bank 3 inverted high intensity Table 3 8 Recommended LUT Values for 1 bpp Color Mode Address Red Green Blue Address Red Green Blue 00 00 00 00 08 00 00 00 01 0F 0F 0F 09 00 00 00 02 00 00 00 0A ...

Page 159: ...r In 8 bpp color mode pixel bits 7 5 represent the red LUT index bits 4 2 represent the green LUT index and bits 1 0 represent the blue LUT index It is recommended that the three LUTs are programmed according to the following format Table 3 10 Recommended LUT Values to Simulate VGA Default 16 Color Palette Address Red Green Blue Address Red Green Blue 00 00 00 00 08 00 00 00 01 00 00 0A 09 00 00 0...

Page 160: ...of 212 4096 colors Gray Shade Modes In gray shade mode the S1D13504 treats the Green LUT as a 16 position 4 bit wide monochrome LUT Depending on the selected pixel size this LUT will provide from 1 to 4 banks 1 bpp Gray Shade The S1D13504 has no true Black and White mode 1 bpp Gray consists of a single bank of two entries For Black and White mode the LUT entry must be programmed as such Table 3 12...

Page 161: ... for 8 bpp gray shade mode bits 7 5 are ignored bits 4 2 represent the green LUT index and bits 1 0 are ignored Only 3 bits of the 8 that actually represent any shade value therefore the maximum gray shade combination is 8 shades If this limitation is deemed appropriate for your application it is recommended that the LUTs are programmed according to the following format Red and Blue LUT entries ar...

Page 162: ...s unimportant The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data Resulting in a maximum of 24 16 colors 16 bpp Gray Shade Since the Look Up Table is bypassed in this mode the LUT programming is unimportant The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data Resulting i...

Page 163: ...This viewport can be panned and scrolled enabling the user to view the entire image The size of the virtual display is limited by the amount of available display buffer In the case of an S1D13504 with 2M byte of display buffer the maximum virtual width ranges from 16 368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode The maximum vertical size at the horizontal maximum is 1025 lines By trading ...

Page 164: ...Offset Registers to support a 16 color 4 bpp 640x480 virtual display on a 320x240 LCD panel To create a virtual display the offset registers must be programmed to the horizontal size of the larger virtual image After determining the amount of memory used by each line do a calculation to see if there is enough memory to support the desired number of lines 1 Initialize the S1D13504 registers for a 3...

Page 165: ...g register allows panning at the pixel level Scrolling requires changing only the start address registers There is an order these registers should be accessed to provide the smoothest apparent movement possible Understanding the sequence of operations performed by the S1D13504 will make it apparent why the order should be followed The start address is latched at the beginning of each frame the pix...

Page 166: ...splay Start Address 0 Start Address Bit 7 Start Address Bit 6 Start Address Bit 5 Start Address Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0 REG 11h Screen 1 Display Start Address 1 Start Address Bit 15 Start Address Bit 14 Start Address Bit 13 Start Address Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 Start Address Bit 8 REG 12h Scr...

Page 167: ...off the values from pan_value for the pixel panning and start address register portions In this case 4 bpp the lower two bits are the pixel panning value and the upper bits are the start address pixel_pan pan_value AND 3 start_address pan_value SHR 3 shift right by 3 gives words 4 Write the pixel panning and start address values to their respective registers using the proce dure outlined in the re...

Page 168: ... Display Start Address and 18h Pixel Panning Register are described in section 4 2 1 on page 26 These two registers form a value known as the line compare When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display When the line compare value is less than the number of physically displayed lines display operation wo...

Page 169: ...0Eh with 0x7C 2 Screen 1 is coming from offset 0 in the display buffer Although not necessary ensure that the screen 1 start address is set to zero Write 0x00 to registers 10h 11h and 12h 3 Calculate the size of the screen 1 image so we know where the screen 2 image is located This calculation must be performed on the virtual size offset register Since a virtual size was not specified assume the v...

Page 170: ... For simplicity we have chosen to use the same time value for power up and power down proce dures The time interval required varies depending on the power supply design The power supply on the S5U13504B00C Evaluation board requires 0 5 seconds to fully discharge Your power supply design may vary Below are the procedures for all cases in which power sequencing is required 5 2 Introduction to Power ...

Page 171: ...s inactive at the same time as LCDPWR If 128 frames is not enough time to allow the LCD Drive power supply to decay to 0V LCDPWR can be controlled manually using REG 1A bit 3 After the 128 frame delay the various clock sources may be disabled depending on the specific application and DRAM Refresh options The actual time for the 128 frame delay can be shortened by using the following example Shorte...

Page 172: ...sociated functionality is automati cally controlled by the internal Power Save circuitry See above for Power Save sequences LCD Enable Disable using Manual Control It may become necessary to enable disable the LCD when switching back and forth to and from the CRT In this case care must be taken when disabling the LCD with respect to the external Power Supply used to provide the LCD Drive voltage T...

Page 173: ... set to access the external RAMDAC Next program the RAMDAC Write Mode Address register and the RAMDAC Palette Data register as desired refer to sample code in 9 1 2 for details When programming the RAMDAC control registers connect the RAMDAC to the low byte of the CPU data bus for Little Endian architecture and the high byte for Big Endian architecture The RAMDAC registers are mapped as follows No...

Page 174: ...evenly Table 6 3 shows the recommended RAMDAC palette data for 8 bpp Simultaneous Display Table 6 4 shows the related register data for some possible CRT options with an 8 bit Color 640X480 single passive panel Table 6 2 Related Register Data for CRT Only Register 640X480 60Hz PCLK 25 175MHz 640X480 75Hz PCLK 31 500MHz 800X600 56Hz PCLK 36 0 MHz 800X600 60Hz PCLK 40 0 MHz Notes REG 04h 0100 1111 0...

Page 175: ...12 3F 2B 09 12 3F 4B 12 12 3F 6B 1B 12 3F 0C 00 1B 00 2C 09 1B 00 4C 12 1B 00 6C 1B 1B 00 0D 00 1B 15 2D 09 1B 15 4D 12 1B 15 6D 1B 1B 15 0E 00 1B 2A 2E 09 1B 2A 4E 12 1B 2A 6E 1B 1B 2A 0F 00 1B 3F 2F 09 1B 3F 4F 12 1B 3F 6F 1B 1B 3F 10 00 24 00 30 09 24 00 50 12 24 00 70 1B 24 00 11 00 24 15 31 09 24 15 51 12 24 15 71 1B 24 15 12 00 24 2A 32 09 24 2A 52 12 24 2A 72 1B 24 2A 13 00 24 3F 33 09 24 3...

Page 176: ...12 3F 8C 24 1B 00 AC 2D 1B 00 CC 36 1B 00 EC 3F 1B 00 8D 24 1B 15 AD 2D 1B 15 CD 36 1B 15 ED 3F 1B 15 8E 24 1B 2A AE 2D 1B 2A CE 36 1B 2A EE 3F 1B 2A 8F 24 1B 3F AF 2D 1B 3F CF 36 1B 3F EF 3F 1B 3F 90 24 24 00 B0 2D 24 00 D0 36 24 00 F0 3F 24 00 91 24 24 15 B1 2D 24 15 D1 36 24 15 F1 3F 24 15 92 24 24 2A B2 2D 24 2A D2 36 24 2A F2 3F 24 2A 93 24 24 3F B3 2D 24 3F D3 36 24 3F F3 3F 24 3F 94 24 2D 0...

Page 177: ...larity and pulse width REG 08h 1000 1111 1101 1111 set vertical display height bits 7 0 REG 09h 0000 0001 0000 0001 set vertical display height bits 9 8 REG 0Ah 0010 1100 0010 1100 set vertical non display period REG 0Bh 0000 0000 0000 1001 set VSYNC start position REG 0Ch 1000 0010 0000 0001 set VSYNC polarity and pulse width REG 0Dh 0000 1111 0000 1111 set 8 bpp and CRT enable REG 19h 0000 0000 ...

Page 178: ...19A G 002 07 Issue Date 01 02 01 7 Identifying the S1D13504 Unlike previous generations of S1D1350x products the S1D13504 can be identified at any time after power on reset The S1D13504 and future S1D1350x products can be identified by reading REG 00h The value of this register for the S1D13504F00A is 04h ...

Page 179: ... a description of the HAL library Updates and revisions to the HAL may include new functions not included in the following documentation 8 2 1 Initialization int seDeRegisterDevice int device Description Removes a device s handle from the HAL library Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid vo...

Page 180: ...forms seRegisterDevice automatically calls seInitHal once Consecutive calls to seRegisterDevice will not call seInitHal again For embedded platforms the startup code which is linked in addition to the HAL library will call seInitHal In this case seInitHal is called before main is called in the application int seRegisterDevice const DeviceInfoDef pDeviceInfo const DEVICE_CHIP_DEF pDeviceChip int De...

Page 181: ...istered device ID Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seValidStdDevice int device Description Determines if the device handle is HAL_STDOUT or HAL_STDIN Parameter device registered device ID Return Value ERR_OK operation completed with no problems ERR_HAL_DEVICE_ERR could not find free device handle 8 2 2 Screen Manipulat...

Page 182: ...ted with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetLastUsableByte int device DWORD pLastByte Description Determines the address of the last byte in the display buffer which can be used by applications Addresses following LastByte are reserved for system use such as the half frame buffer for dual panels It is assumed that the registers have already been correctly init...

Page 183: ...n bytes from start of the display buffer pByte returns value of byte Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seReadDisplayWord int device DWORD offset WORD pWord Description Reads a word from the display buffer Parameter device registered device ID offset offset in bytes from start of the display buffer pWord returns value of...

Page 184: ...crn2Addr starting address of bottom image addr 0 refers to beginning of the display buffer Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seSetInit must first be called before calling seSplitInit This is because the VNDP is used for timing and this would not be possible if the registers were not first initialized int seSplitScreen ...

Page 185: ... 0x3ff The maximum allowable xVirt is 0x3ff 16 bpp If bpp is 15 use the above equation with bpp 16 Note seSetInit must have been called before calling seVirtInit This is because the VNDP is used for timing and this would not be possible if the registers were not first initialized int seVirtMove int device BYTE WhichScreen int x int y Description Pans or scrolls the virtual display Parameter device...

Page 186: ...ayWords int device DWORD addr WORD val DWORD count Description Writes one or more words to the display buffer Parameter device registered device ID addr offset from start of the display buffer val value to write count number of words to write Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seWriteDisplayDwords int device DWORD addr D...

Page 187: ...DacEntry int device BYTE index BYTE pEntry Description Reads one DAC entry Parameter device registered device ID index index to DAC entry 0 to 255 pEntry pointer to an array of BYTE entry 3 entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGetLut int device BY...

Page 188: ...int device BYTE pDac Description Writes the entire DAC from an array into the DAC registers Parameter device registered device ID pDac pointer to an array of BYTE dac 256 3 dac x 0 RED component dac x 1 GREEN component dac x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetDacEntry int device BYTE index BYTE pEnt...

Page 189: ...device registered device ID index index to LUT entry 0 to 15 pEntry pointer to an array of BYTE entry 3 entry x 0 RED component entry x 1 GREEN component entry x 2 BLUE component Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seGet15BppInfo int device unsigned RedMask unsigned GreenMask unsigned BlueMask Description Determines the b...

Page 190: ...ithin a WORD Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seDrawLine only draws horizontal and vertical lines and that the line drawn does not include the endpoint x2 y2 int seDrawText int device char fmt Description For Intel platforms draws text to standard output For embedded platforms draws text to terminal Parameter device r...

Page 191: ...hin a WORD Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid Note seFillRect does not fill the rectangle s right and bottom sides int seGetchar void Description Gets a character from platform typically from a terminal Parameter none Return Value Character returned from platform int sePutchar int ch Description Writes a character to platfor...

Page 192: ... device ID index register index pVal returns value of the register Return Value ERR_OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seSetReg int device int index BYTE val Description Writes a register value Parameter device registered device ID index register index val value to write to the register Return Value ERR_OK operation completed with no pro...

Page 193: ... left as many times as stated in bits Parameter val value to rotate bits how many bits to rotate Return Value bits 15 8 non zero if carry flag set bits 7 0 rotated byte WORD seRotateByteRight BYTE val BYTE bits Description Rotates the bits in val right as many times as stated in bits Parameter val value to rotate bits how many bits to rotate Return Value bits 15 8 non zero if carry flag set bits 7...

Page 194: ...e for example purposes only 9 1 1 Sample code using 13504HAL API Created 1998 Epson Research Development Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All rights reserved include stdio h include stdlib h include string h include hal h include appcfg h void main void BYTE ChipId int Device switch seRegisterDevice Cfg DeviceInfo 0 Cfg DeviceChip Device case ERR_OK break...

Page 195: ...e demonstrating the initialization of the S1D13504 Beta release 2 0 98 10 22 The code in this example will perform initialization to the following specification 320 x 240 single 8 bit color passive panel 75 Hz frame rate 8 BPP 256 colors 33 MHz input clock 2 MB of 60 ns FPM memory This is sample code only This means 1 Generic C is used I assume that pointers can access the relevant memory addresse...

Page 196: ...998 Epson Research and Development Inc All rights reserved Header Revision Log unsigned char LUT8 8 3 0x00 0x00 0x00 0x02 0x02 0x05 0x04 0x04 0x0A 0x06 0x06 0x0F 0x09 0x09 0x00 0x0B 0x0B 0x00 0x0D 0x0D 0x00 0x0F 0x0F 0x00 REGISTER_OFFSET points to the starting address of the S1D13504 registers define REGISTER_OFFSET unsigned char 0x1234 void main void unsigned char pRegs unsigned char pLUT int idx...

Page 197: ...2 Performance Enhancement pRegs 0x22 0x24 0010 0100 Step 5 Set dual single panel Register 2 Panel Type 8 bit format 2 color single passive pRegs 0x02 0x1C 0001 1100 Step 6 Set the rest of the registers in order Register 3 Mod Rate pRegs 0x03 0x00 0000 0000 Register 4 Horizontal Display Width HDP 320 pixels 320 8 1 39t 27h pRegs 0x04 0x27 0010 0111 Register 5 Horizontal Non Display Period HNDP PCLK...

Page 198: ...he frame rate closest to the desired frame rate pRegs 0x0A 0x01 0000 0001 Register B VRTC FPFRAME Start Position applicable to CRT TFT only pRegs 0x0B 0x00 0000 0000 Register C VRTC FPFRAME Pulse Width applicable to CRT TFT only pRegs 0x0C 0x00 0000 0000 Registers E F Screen 1 Line Compare unless setting up for split screen operation use 0x3FF pRegs 0x0E 0xFF 1111 1111 pRegs 0x0F 0x03 0000 0011 Re...

Page 199: ...on enable LCD power CBR refresh not suspended pRegs 0x1A 0x00 0000 0000 Register 1C 1D MD Configuration Readback don t write anything to these registers Register 1E 1F General I O Pins Configuration these values may need to be changed according to your system pRegs 0x1E 0x00 0000 0000 pRegs 0x1F 0x00 0000 0000 Register 20 21 General I O Pins Control these values may need to be changed according to...

Page 200: ... idx 0 idx 8 idx for rgb 0 rgb 3 rgb pRegs 0x26 pLUT pLUT Registers 28 2E RAMDAC not used in this example Programmed very similarly to the LUT but all 256 entries are used Register 23 Performance Enhancement display FIFO enabled optimum performance pRegs 0x23 0x10 0001 0000 Register D Display Mode 8 BPP LCD enable pRegs 0x0D 0x0D 0000 1101 ...

Page 201: ...G 0Dh 0000 1101 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0110 0000 0110 0000 0001 0000 0001 0000 0001 set MCLK and PCLK divide REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load LUT load LUT load Look Up Table REG 27h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table...

Page 202: ...od REG 06h 0000 0110 set HSYNC start position REG 07h 0000 0111 set HSYNC polarity and pulse width REG 08h 1101 1111 set vertical display height bits 7 0 REG 09h 0000 0001 set vertical display height bits 9 8 REG 0Ah 0010 1101 set vertical non display period REG 0Bh 0000 0000 set VSYNC start position REG 0Ch 0000 0010 set VSYNC polarity and pulse width REG 0Dh 0000 1101 set 8 bpp and LCD enable RE...

Page 203: ...PLAY S TART A DDRESS R EGISTER 2 RW n a n a n a n a Screen 2 Display Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 16h M EMORY A DDRESS O FFSET R EGISTER 0 RW Memory Address Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 17h M EMORY A DDRESS O FFSET R EGISTER 1 RW n a n a n a n a n a n a Memory Address Offset Bit 9 Bit 8 REG 18h P IXEL P ANNING R EGISTER RW Screen 2 Pixel Panning Scree...

Page 204: ...ion 00 Normal 01 Line Doubling 10 Interlace 11 Even Scan Only Number Of Bits Pixel Select Bits 2 0 Number of Bits Pixel 000 1 001 2 010 4 011 8 100 15 101 16 110 111 Reserved PCLK Divide Select Bits 1 0 MCLK PCLK Frequency Ratio 00 1 01 2 10 3 11 4 Suspend Refresh Select Bits 1 0 DRAM Refresh Type 00 CBR Refresh 01 Self Refresh 1x No Refresh RC Timing Bits 1 0 Minimum Random Cycle Width 00 5 MCLK ...

Page 205: ...S1D13504 Color Graphics LCD CRT Controller 13504CFG EXE Configuration Program Document Number X19A B 001 04 ...

Page 206: ...d and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trade...

Page 207: ...Epson Research and Development Page 3 Vancouver Design Center 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 THIS PAGE LEFT BLANK ...

Page 208: ...3504CFG EXE 7 Program Requirements 8 Installation 8 Usage 8 Script Mode 9 Interactive Mode 10 13504CFG Menu Bar 10 Viewing 13504CFG Menu Contents 10 Making 13504CFG Menu Selections 11 Files Menu 12 View Menu 13 Device Menu 15 Panel 16 CRT 18 Advanced Memory 20 Power Management 22 Lookup Table LUT 24 Setup 26 Help Menu 27 Comments 28 Sample Program Messages 28 ...

Page 209: ...Epson Research and Development Page 5 Vancouver Design Center 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 THIS PAGE LEFT BLANK ...

Page 210: ...3504CFG Edit Panel Setup 17 Figure 10 13504CFG Panel Parameter Edit 17 Figure 11 13504CFG CRT Setup 18 Figure 12 13504CFG Edit CRT Setup 19 Figure 13 13504CFG CRT Parameter Edit 19 Figure 14 13504CFG Advanced Memory Setup 20 Figure 15 13504CFG Edit Advanced Memory Setup 21 Figure 16 13504CFG Memory Parameter Edit 21 Figure 17 13504CFG Power Setup 22 Figure 18 13504CFG Edit Power Setup 23 Figure 19...

Page 211: ...Epson Research and Development Page 7 Vancouver Design Center 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 THIS PAGE LEFT BLANK ...

Page 212: ...odes one mode reads script files and the other mode is interactive In the interactive mode the 13504CFG DOS based program uses an interface similar to Windows to present one menu for each configuration section Each section has its own dialog box showing all of the relevant elements for that section 13504CFG reads the configuration from a specific EXE file for Intel platforms and from a specific S9...

Page 213: ...rogram is intended to run independent of 13504CFG Usage At the DOS Prompt type 13504cfg 13504cfg exe filename exe script ini Where filename exe is the 13504 utility to be modified script ini is the list of HAL configuration changes see See Script Mode on page 10 displays the usage screen no argument runs 13504CFG in the interactive mode Video Controller Any VGA Display Type LCD or CRT BIOS Any man...

Page 214: ...ssary to list all of the possible items in the script file For example if the script is only to change the panel resolution the script would only have the following lines File TEST INI Panel x 640 Panel y 480 To use this script file on the 13504PLAY utility type the following 13504CFG 13504PLAY EXE TEST INI In this example all of the other panel settings in the 13504 utility remain the same In gen...

Page 215: ... Menu contents can be viewed by using either the mouse or the keyboard Viewing 13504CFG Menu Contents Mouse Move the on screen arrow with the mouse and point at the desired menu Click the left mouse button and the contents of the menu will be displayed Keyboard Press Alt F to select the Files menu Alt V to select the View menu Alt D to select the Device menu Alt H to select the Help menu or the hi...

Page 216: ...ways to select and open 13504SHOW EXE in the Files box in the Open File window figure 2 Mouse Click the left mouse button on 13504SHOW EXE to highlight it in the Files box Then click on the OK button Point to the file 13504SHOW EXE with the arrow and click the left mouse button twice in rapid succession double clicking Keyboard Press Tab to highlight the Files box or press Alt F Press to highlight...

Page 217: ...ity Note A utility must be opened before any other menu command can be executed Save saves the current changes to the opened file Save As saves a file to a different name and or different location Save All saves modifications to all 13504 files that are in the same directory as the file being saved This function ensures that the display parameters are consistent Save All is only avail able for uti...

Page 218: ...ement Look Up Table and Setup sub menus in the Device menu Some configuration parameters cannot be readily changed as they depend on several factors for consistency eg Frame Rate Clock Divides etc Refer to the S1D13504 Functional Hardware Specification manual document number X19A A 002 xx and the S1D13504 Programming Notes and Examples manual document number X19A G 002 xx for formulas and other in...

Page 219: ...velopment Page 15 Vancouver Design Center 13504CFG EXE Configuration Program S1D13504 Issue Date 01 01 30 X19A B 001 04 Figure 5 13504CFG Current Configuration Figure 6 13504CFG Advanced Configuration Partial View of Screen ...

Page 220: ...3504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 Device Menu Figure 7 13504CFG Device Menu The Device menu contains the following sub menus where parameters for a S1D13504 utility can be edited Panel CRT Advanced Memory Power Management Look Up Table Setup ...

Page 221: ...ono Single 320x240 is highlighted and click OK If the highlighted panel assignment needs changes click Edit and see the next section Edit Panel Setup Whenever a panel assignment is edited or selected in the Panel Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command...

Page 222: ... parameters which can be edited as shown below in Figure 9 13504CFG Edit Panel Setup In this example window X Resolution 320 pixels is highlighted Figure 9 13504CFG Edit Panel Setup Panel Parameter Edit When a selection is highlighted for editing in the Edit Panel Setup window and Edit is clicked the Panel Parameter Edit window displays for parameter editing See figure 10 13504CFG Panel Parameter ...

Page 223: ...Hz CLKI 33 333MHz is highlighted and click OK If the highlighted CRT assignment needs changes click Edit and see the next section Edit CRT Setup Whenever a CRT assignment is edited or selected in the CRT Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command is liste...

Page 224: ...rameters which can be edited as shown below in Figure 12 13504CFG Edit CRT Setup In this example window Horiz Non Display 240 pixels is highlighted Figure 12 13504CFG Edit CRT Setup CRT Parameter Edit When a selection is highlighted for editing in the Edit CRT Setup window and Edit is clicked the CRT Parameter Edit window displays for parameter editing See figure 13 13504CFG CRT Parameter Edit bel...

Page 225: ...Memory Type 0 is highlighted and click OK If the highlighted memory assignment needs changes click Edit and see the next section Edit Memory Setup Whenever a memory assignment is edited or selected in the Memory Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configu ration In addition to OK Cancel and Edit commands a Help command...

Page 226: ...ers which can be edited as shown below in Figure 15 13504CFG Edit Advanced Memory Setup In this example window Refresh Time 4000 Cycles is highlighted Figure 15 13504CFG Edit Advanced Memory Setup Memory Parameter Edit When a selection is highlighted for editing in the Edit Advanced Memory Setup window and Edit is clicked the Memory Parameter Edit window is displayed for parameter editing See figu...

Page 227: ... below Power Type 0 is highlighted and click OK If the highlighted power assignment needs changes click Edit and see the next section Edit Power Setup Whenever a power assignment is edited or selected in the Power Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configu ration In addition to OK Cancel and Edit commands a Help comma...

Page 228: ...meters which can be edited as shown below in Figure 18 13504CFG Edit Power Setup In this example window Suspend Refresh CBR Refresh is highlighted Figure 18 13504CFG Edit Power Setup Power Parameter Edit When a selection is highlighted for editing in the Edit Power Setup window and Edit is clicked the Power Parameter Edit window displays for parameter editing See figure 19 13504CFG Power Parameter...

Page 229: ...elow LUT Internal 4 Color is highlighted and click OK If the highlighted LUT assignment needs changes click Edit and see the next section Edit LUT Setup Whenever a LUT assignment is edited or selected in the LUT Setup dialog box the setup is copied to Current Configuration The editing is automatically performed on the current configuration In addition to OK Cancel and Edit commands a Help command ...

Page 230: ... In this example window Bits Per Pixel 2 is highlighted Note A future release of 13504CFG will enable components in the lookup table palette to be edited For example the red green and blue components of LUT palette entry 0Fh could be edited Figure 21 13504CFG Edit LUT Setup LUT Parameter Edit When a selection is highlighted for editing in the Edit LUT Setup window and Edit is clicked the LUT Param...

Page 231: ... either Register Location Memory Location or Memory Size highlight it in the example window below Register Location 00C00000 hex is highlighted and click OK If the highlighted Setup assignment needs changes click Edit and see the next section Setup Parameter Edit In addition to OK Cancel and Edit commands a Help command is listed in the Setup windows In this version of 13504CFG the Help files are ...

Page 232: ...window is displayed for parameter editing The Setup Parameter Edit windows for Register Location Memory Location and Memory Size respectively are shown below Figure 24 13504CFG Setup Parameter Edit For Register Location Memory Location and Memory Size Help Menu There are three files in the Help menu Help not available in this version of 13504CFG Help on Help not available in this version of 13504C...

Page 233: ...ormation In addition the 13504CFG user must know the hardware setup for the panel and CRT and the setup for the given hardware platform such as memory addresses and memory speed Sample Program Messages ERROR Could not open filename Could not open the 13504 utility called filename This message is generated from the command line 13504CFG filename script ini ILLEGAL VALUE Choose between 8 and 800 in ...

Page 234: ...Page 30 Epson Research and Development Vancouver Design Center S1D13504 13504CFG EXE Configuration Program X19A B 001 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 235: ...cument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Eps...

Page 236: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504SHOW Demonstration Program X19A B 002 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 237: ...ram to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection S1D13504 Supported Evaluation Platforms 13504SHOW has been tested with the following S1D13504 supported evaluation platforms PC syste...

Page 238: ...en using a dual panel refer to the Maximum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to...

Page 239: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 240: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504SPLT Display Utility X19A B 003 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 241: ...a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ether...

Page 242: ...ing keyboard commands are for navigation within the program Manual mode moves Screen 2 up moves Screen 2 down HOME covers Screen 1 with Screen 2 END displays only Screen 1 Automatic mode Z changes the direction of split screen movement Both modes B changes the color depth bits per pixel ESC exits 13504SPLT 13504SPLT Example 1 Type 13504splt a to automatically move the split screen 2 Press b to cha...

Page 243: ... is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached Program Messages ERROR Too many devices registered There are too many display devices attached ...

Page 244: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 13504SPLT Display Utility X19A B 003 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 245: ...ent but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson ...

Page 246: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504VIRT Display Utility X19A B 004 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 247: ... done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection S1D13504 Supported Evaluation Platforms 13504VIRT has been tested wit...

Page 248: ... width of the virtual display The following keyboard commands are for navigation within the program Manual mode scrolls up scrolls down pans to the left pans to the right HOME moves the display screen so that the upper right of the virtual screen shows in the upper right of the display END moves the display screen so that the lower left of the virtual screen shows in the lower left of the display ...

Page 249: ...select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing A CRT cannot show 15 or 16 bits per pixel Do not attach a panel with a 16 bit interface to the S1D13504 when a CRT is also attached Program Messages ERROR Too many...

Page 250: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 13504VIRT Display Utility X19A B 004 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK ...

Page 251: ...ment but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson...

Page 252: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504PLAY Diagnostic Utility X19A B 005 05 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 253: ...or the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also comm...

Page 254: ... bytes 1 red 1 green 1 blue DA Reads all DAC values L index data1 data2 data3 Reads writes Look Up Table LUT values Writes data to the LUT index when data is specified otherwise the LUT index is read Data consists of 3 bytes 1 red 1 green 1 blue LA Reads all LUT values F W addr1 addr2 data Fills bytes or words from address 1 to address 2 with data Data can be multiple values e g F 0 20 1 2 3 4 fil...

Page 255: ... write 10 hex to register 3 7 Type f 0 ffff aa to fill the first FFFF hex bytes of display memory with AA hex 8 Type f 0 1fffff aa to fill 2M bytes of display memory 9 Type r 0 ff to read the first 100 hex bytes of display memory 10 Type q to exit the program Scripting 13504PLAY can be driven by a script file This is useful when there is no display output and a current register status is required ...

Page 256: ...mum Frame Rates table in the S1D13504 Functional Hardware Specification document number X19A A 002 xx When editing in 13504CFG with CRT enabled and panel disabled select Single Panel from the Edit Panel Setup submenu When a CRT is enabled the CRT settings will override the panel settings If a panel is also used the CRT timing values will have to be changed to more closely match the panel s timing ...

Page 257: ...ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epso...

Page 258: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504BMP Demonstration Program X19A B 006 04 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 259: ...seconds lcd displays the image on a LCD crt displays the image on a CRT displays the Help screen Comments 13504BMP only currently decodes Windows BMP format images The PC must not have more than 12M bytes of memory when used with the S5U13504B00C board Follow simultaneous display guidelines for correct simultaneous display operation To determine if the CRT will operate correctly when using a dual ...

Page 260: ...o the HAL The HAL can only manage 10 devices simultaneously ERROR Could not register S1D13504 device A 13504 device was not found at the configured addresses Check the configuration address using the 13504CFG configuration program ERROR Did not detect S1D13504 The HAL was unable to read the revision code register on the S1D13504 Ensure that the S1D13504 hardware is installed and that the hardware ...

Page 261: ...e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of ...

Page 262: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A B 007 04 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 263: ...ware from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection S1D13504 Sup...

Page 264: ...uments software disable To enable the LCD use the following arguments lcd enable To disable the LCD use the following arguments lcd disable Comments The i argument is to be used when the registers have not been previously initialized The PC must not have more than 8M bytes of memory when used with the S5U13504B00B board Follow simultaneous display guidelines for correct simultaneous display operat...

Page 265: ...ected DISABLE Command line argument disable was selected more than once Select disable only once ERROR Select software or hardware Neither command line argument software or hardware was selected Select software or hardware ERROR Select enable or disable Neither command line argument enable or disable was selected Select enable or disable ERROR Too many devices registered There are too many display...

Page 266: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 13504PWR Software Suspend Power Sequencing Utility X19A B 007 04 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 267: ...in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Wind...

Page 268: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 269: ...0 26 X19A B 008 03 Table of Contents 13504DCFG 5 Installation 6 Usage 6 13504DCFG Configuration Tabs 7 General Tab 7 Preferences Tab 9 Memory Tab 10 Clocks Tab 13 Panel Tab 15 CRT Tab 19 Registers Tab 20 13504DCFG Menus 21 Export 21 Enable Tooltips 22 ERD on the Web 22 Update Common Controls 22 About 13504DCFG 22 Comments 23 ...

Page 270: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 271: ...t generates C header files containing user specified display configurations The header files are intended to be used by a software hardware developer in the development of display drivers Note It is possible to override recommended register settings and select incorrect panel tim ings using 13504DCFG Seiko Epson does not assume liability for any damage done to the display device as a result of con...

Page 272: ...r from a Windows command prompt To start 13504DCFG from the Windows desktop double click the program icon in the directory which the program was installed To start 13504DCFG from a Windows command prompt change to the directory 13504dcfg exe was installed to and type the command 13504dcfg The basic procedure for using 13504DCFG is 1 Start 13504DCFG as described above 2 Modify the configuration set...

Page 273: ...eneral tab contains S1D13504 evaluation platform specific information The values presented are used for configuring HAL based display drivers The settings on this tab specify where in CPU address space the registers and display buffer are located and the data bus size Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer ad...

Page 274: ...ister Address The physical address of the start of register decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Display Buffer Address The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode...

Page 275: ...e initial display state During runtime the display surface or color depth may be changed by software Initial Display Sets which display device is used for the initial display Selections made on the CRT and Panel tabs may cause selections on this tab to be grayed out The selections None and Panel are always available Panel Color Depth Sets the initial color depth on the LCD panel Initial Display Pa...

Page 276: ...optimal memory clock Memory Configuration These settings must be configured based on the specifi cation of the DRAM being used For each of the following settings refer to the DRAM manufacturer s specification unless otherwise noted Memory Clock The current Memory Clock MCLK frequency is displayed here Access Time Selects the access time of the DRAM The S1D13504 evaluation boards use 50ns DRAM Memo...

Page 277: ...imize the memory timings for best performance The default values change based on the memory configuration access time memory type etc For further information on configuring these settings refer to the S1D13504 Hardware Functional Specifi cation document number X19A B 001 xx and the DRAM manufacturer s specification Suspend Mode Refresh Selects the DRAM refresh method used during power save mode CA...

Page 278: ...ncouver Design Center S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 Installed Memory Selects the amount of DRAM available for the display buffer The S1D13504 evaluation boards have 2M bytes of DRAM installed ...

Page 279: ...umber X19A B 001 xx Note Changing clock values may modify or invalidate Panel or CRT settings Confirm all set tings on these two tabs after changing any clock settings CLKI These controls are used to inform 13A04DFGC of the clock frequency attached to CLKI Setting incorrect values will result in errors in the rest of the configu ration process Timing Use this control to set the CLKI frequency by s...

Page 280: ...om the dropdown control If the dropdown does not contain the exact frequency then the frequency can be typed into the edit box Actual This field displays the BUSCLK frequency that 13A04DFG will use for configuration calculations PCLK The PCLK controls allow adjustment of the pixel clock PCLK frequency Source PCLK source is always MCLK Divide Set the MCKL divide ratio to derive PCLK Timing Displays...

Page 281: ...sions type and timings Panel Type Selects between passive STN and active TFT panel types Several options may change or become unavailable when the STN TFT setting is switched Therefore confirm all settings on this tab after the Panel Type is changed Panel Type Panel Dimensions TFT FPLINE TFT FPFRAME Panel Data Width FPLINE FPFRAME Frame Rate Pixel Clock Predefined Panels Polarity Polarity Non Disp...

Page 282: ...ono Color Selects between a monochrome or color panel Single Dual Selects between a single or dual panel When the panel type is TFT Single is automatically selected and the Dual option is grayed out Half Frame Buffer Enable The Half Frame Buffer is used with dual STN panels to improve image quality by buffering display data in a format directly usable by the panel This option is primarily intended...

Page 283: ...te Displays the current Frame Rate based on clock and panel parameters Pixel Clock Displays the current PCLK Frequency as set in the Clocks tab TFT FPLINE pixels These settings allow fine tuning the TFT line pulse parameters and are only available when the selected panel type is TFT Refer to S1D13504 Hardware Functional Specification document number X19A B 001 xx for a complete description of the ...

Page 284: ...f the FPFRAME output signal Predefined Panels 13504DCFG uses a file panels def which lists various panel manufacturers recommended settings If the file panels def is present in the same directory as 13504dcfg exe the settings for a number of predefined panels are available in the drop down list If a panel is selected from the list 13504DCFG loads the predefined settings contained in the file ...

Page 285: ... the Clocks tab must be changed Simultaneous Display Options When both the LCD and CRT are operating in simulta neous display mode a method of displaying both images must be selected based on the vertical resolution height of the images If both displays are the same resolution select Normal Otherwise refer to the S1D13504 Hardware Functional Specification document number X19A B 001 xx for informat...

Page 286: ...ttings may be changed by double clicking on the register in the list Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the S1D13504 Hardware Functional Specification document number X19A B 001 xx be referred to before making an manual register settings Manually entered values may be changed by 13504...

Page 287: ...rs for other operating systems such as Linux QNX and VxWorks UGL or WindML A comma delimited text file containing an offset a value and a description for each S1D13504 register An HTML file containing a Register Quick Reference After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configur...

Page 288: ...ooltip appears ERD on the Web This Help menu item is a hotlink to the Epson Research and Development website Selecting Help then ERD on the Web starts the default web browser and points it to the ERD web site The latest software drivers and documentation for the S1D13504 is available at this website Update Common Controls Many of the dialog controls used by 13504DGFG require the latest version of ...

Page 289: ...emely low CLKI frequen cies on the Clocks tab may result in no possible CRT options Selecting TFT or STN on the Panel tab enables disables options specific to the panel type The file panels def is a text file containing operational specifications for several supported and tested panels This file can be edited with any text editor 13504DCFG allows manually altering register values The manual change...

Page 290: ...Page 24 Epson Research and Development Vancouver Design Center S1D13504 13504DCFG Driver Configuration Program X19A B 008 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 291: ...uating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are...

Page 292: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Windows CE 2 x Display Drivers X19A E 001 05 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 293: ...rosoft Windows CE 2 x operating system The driver is capable of 4 8 and 16 bit per pixel display modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciat...

Page 294: ...oject by following the procedure documented in Creating a New Project Directory from the Windows CE ETK V2 0 Alternately use the current DEMO7 project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu...

Page 295: ...4 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODE0 H for the default settings of the driver If the default does not match the configuration you are building for then MODE0 H will have to be regenerated with the correct informa ...

Page 296: ...le project icon i e X86 DEMO7 13 Type BLDDEMO ENTER at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriate 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Ins...

Page 297: ...xcopy s e x wince public maxall wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13504 1 echo off 6 Make an S1D13504 directory under x wince platform cepc drivers display and copy the S1D13504 driver source code into x wince platform cepc drivers dis play S1D13504 7 Edit the file x wi...

Page 298: ...User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODE0 H in x wince platform cepc drivers display S1D13504 replacing the original configura tion file 10 Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display...

Page 299: ...ay Drivers S1D13504 Issue Date 01 05 25 X19A E 001 05 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO ENTER at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN ...

Page 300: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 301: ...isplay driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable _WINCEOSVER is not defined then WINCEVER will default 2 11 The display driver may test against this option to support different WinCE version specific features EpsonMessages Thi...

Page 302: ...ou do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S1D13504 Width dword 280 Height dword 1E0 Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 2 Note that all dword values are in hex...

Page 303: ...al Windows CE Platform Builder supported platforms When using 13504CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been run with version 2 0 of the ETK ...

Page 304: ...Page 14 Epson Research and Development Vancouver Design Center S1D13504 Windows CE 2 x Display Drivers X19A E 001 05 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 305: ...ocument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Ep...

Page 306: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Wind River WindML v2 0 Display Drivers X19A E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 307: ...s generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13504DCFG see the 13504DCFG Configuration Program User Manual document number X19A B 008 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to de...

Page 308: ...kette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13504 8bpp File config h or x 13504 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file r...

Page 309: ... driver source code uses single line comment notation rather than the ANSI conventional comments To add support for single line comments follow these steps a In the Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Propertie...

Page 310: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Wind River WindML v2 0 Display Drivers X19A E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 311: ...valuating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ...

Page 312: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Wind River UGL v1 2 Display Drivers X19A E 003 02 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 313: ...cient driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks addresses etc by OEMs For further infor mation on 13504DCFG see the 13504DCFG Configuration Program User Manual document number X19A B 008 xx This do...

Page 314: ...Replace the file x Tornado target config pcPentium config h with the file x 13504 8bpp File config h or x 13504 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the To...

Page 315: ... Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A properties win dow will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for det...

Page 316: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Wind River UGL v1 2 Display Drivers X19A E 003 02 Issue Date 01 02 01 THIS PAGE LEFT BLANK ...

Page 317: ...download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registere...

Page 318: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Linux Console Driver X19A E 004 01 Issue Date 01 11 19 THIS PAGE LEFT BLANK ...

Page 319: ... is generated by the configuration utility 13504DCFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13504DCFG see the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx Note The Linux console driver is provided as reference source code only The driver is in tended to provide a basis for...

Page 320: ...able on www erd epson com was built using Red Hat Linux 6 1 kernel version 2 2 17 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13504 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D1...

Page 321: ...3504DCFG refer to the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx available at www erd epson com After selecting the desired configuration choose File Export and select the C Header File for S1D13504 Generic Drivers option Save the new configuration as s1d13504 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video ...

Page 322: ...he lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13504 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfr...

Page 323: ...erd epson com was built using Red Hat Linux 6 1 kernel version 2 4 5 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13504 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13504 archive ...

Page 324: ...rmation Use the program 13504DCFG to generate the required header file For information on how to use 13504DCFG refer to the 13504DCFG Driver Configuration Program User Manual document number X19A B 008 xx available at www erd epson com After selecting the desired configuration choose File Export and select the C Header File for S1D13504 Generic Drivers option Save the new configuration as s1d13504...

Page 325: ... to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13504 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the neces...

Page 326: ...Page 10 Epson Research and Development Vancouver Design Center S1D13504 Linux Console Driver X19A E 004 01 Issue Date 01 11 19 THIS PAGE LEFT BLANK ...

Page 327: ...uating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are...

Page 328: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Windows CE 3 x Display Drivers X19A E 006 01 Issue Date 01 05 08 THIS PAGE LEFT BLANK ...

Page 329: ...t Windows CE operating system version 3 0 The driver is capable of 4 8 and 16 bit per pixel display modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We apprec...

Page 330: ...ng on the Microsoft Windows CE Platform Builder icon 4 Create a new project a Select File New b In the dialog box select the Platforms tab c In the platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC ...

Page 331: ...he Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WI...

Page 332: ...rogram User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 12 From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Param...

Page 333: ...n oak misc call wince x86 i486 CE MINSHELL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 4 Generate the build environment by calling cepath bat 5 Create a new folder called S1D13504 under x wince300 platform cepc drivers dis play and copy the S1D13504 driver source code into x wince300 platform cepc driv ers display S1D13504 6 Edit the file x wince300 platform cepc drivers displa...

Page 334: ...information on how to use 13504CFG refer to the 13504CFG Configuration Program User Manual document number X19A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13504 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 9 Edit the file PL...

Page 335: ...vers S1D13504 Issue Date 01 05 08 X19A E 006 01 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO ENTER at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin ...

Page 336: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 337: ...n specific features EnablePreferVmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option for systems with 512K bytes of video memory and VGA 640x480 panels ENABLE_ANTIALIASED_FONTS This option enables the display driver support of antialiased fo...

Page 338: ...register information to control the desired display mode The MODE tables must be generated by the configuration program 13504CFG EXE The display driver comes with example MODE tables By default only MODE0 H is used by the display driver New mode tables can be created using the 13504CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode yo...

Page 339: ...erformance and power off capabilities The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of Windows CE Display Driver ...

Page 340: ... mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is L...

Page 341: ...ay Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S1D13504 sources and change the line CDEF...

Page 342: ... several Windows CE Platform Builder supported platforms If you are running 13504CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number At this time the drivers have been tested on the x86 CPUs and have been built with Plat fo...

Page 343: ...ut only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corpo...

Page 344: ...Page 2 Epson Research and Development Vancouver Design Center S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 THIS PAGE LEFT BLANK ...

Page 345: ...y of LCD controllers with Windows NT 4 0 2000 The file S1D13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Installation Windows NT Version 4 0 All evaluation boards require the driver to be installed as follows 1 Install the evaluation board in the computer and boot th...

Page 346: ...nd it 7 Click NEXT 8 Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN 9 Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT 3 Select ADD ...

Page 347: ...ows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Go to the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ...

Page 348: ... Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 Click NEXT Windows will search the floppy drive and fail 4 Windows will attempt to load the new hardware as a Standard VGA Card 5 Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE 6 Select NO for Windows to DETECT NEW HARDWARE 7 Click NEXT 8 Select OTHER DEVICES from HARDWARE TYPE a...

Page 349: ...lick NEXT 5 Select OTHER DEVICES and click NEXT 6 Click Have Disk 7 Specify the location of the driver files and click OK 8 Click Next 9 Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Windows will detect the card 3 Select DRIVER FROM DISK PROVIDED BY MANUFACTURER 4 Click OK 5 Specify a path to the loc...

Page 350: ...he computer and boot the computer 2 Go to the CONTROL PANEL and select ADD NEW HARDWARE 3 Click NEXT 4 Select NO and click NEXT 5 Select OTHER DEVICES from the HARDWARE TYPES list 6 Click HAVE DISK 7 Specify the location of the driver files and click OK 8 Select the file S1D13XXX INF and click OK 9 Click OK 10 The EPSON PCI Bridge Card should be selected in the list window 11 Click NEXT 12 Click N...

Page 351: ...d use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark...

Page 352: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 353: ...ical Description 13 6 1 ISA Bus Support 13 6 2 Non ISA Bus Support 14 6 3 DRAM Support 14 6 4 Decode Logic 14 6 5 Clock Input Support 14 6 6 Monochrome LCD Panel Support 15 6 7 Color Passive LCD Panel Support 15 6 8 Color TFT LCD Panel Support 15 6 9 External CMOS RAMDAC Support 15 6 10 Power Save Modes 16 6 11 Core VDD Power Supply 16 6 12 IO VDD Power Supply 16 6 13 Adjustable LCD Panel Negative...

Page 354: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 355: ...s 8 Table 3 1 LCD Signal Connector J6 9 Table 4 1 CPU BUS Connector H1 Pinout 10 Table 4 2 CPU BUS Connector H2 Pinout 11 Table 5 1 Host Bus Interface Pin Mapping 12 List of Figures Figure 1 S1D13504B00C Schematic Diagram 1 of 6 20 Figure 2 S1D13504B00C Schematic Diagram 2 of 6 21 Figure 3 S1D13504B00C Schematic Diagram 3 of 6 22 Figure 4 S1D13504B00C Schematic Diagram 4 of 6 23 Figure 5 S1D13504B...

Page 356: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 357: ...cation document number X19A A 002 xx 1 1 Features 128 pin QFP15 package SMT technology for all appropriate devices 4 8 bit monochrome passive LCD panels support 4 8 16 bit color passive LCD panels support 9 12 18 bit LCD TFT panels support External RAMDAC support 16 bit ISA bus support Oscillator support for CLKI up to 40 0MHz 5 0V 1M x 16 EDO DRAM Support for software power save modes 3 3V Core V...

Page 358: ...gh open 0 or low Table 2 1 Configuration DIP Switch Settings Switch Signal Closed Open SW1 1 MD1 See Host Bus Selection table below See Host Bus Selection table below SW1 2 MD2 SW1 3 MD3 SW1 4 MD4 Little Endian Big Endian SW1 5 MD5 Wait signal is active high Wait signal is active low required settings for ISA bus support Table 2 2 Host Bus Selection MD3 MD2 MD1 Option Host Bus Interface 0 0 0 1 SH...

Page 359: ... UD3 FPDAT8 17 B0 B1 B3 LD4 FPDAT9 19 R0 R2 LD5 DACP7 FPDAT10 21 R1 LD6 DACP6 FPDAT11 23 G0 G2 LD7 DACP5 FPDAT12 25 G1 UD4 DACP4 FPDAT13 27 G0 UD5 DACP3 FPDAT14 29 B0 B2 UD6 DACP2 FPDAT15 31 B1 UD7 DACP1 FPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT DRDY 35 FPSHIFT2 FPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPFRAME 39 FPFRAME FPFRAME FPFRAME FPF...

Page 360: ...nected to DB6 of the S1D13504 10 Connected to DB7 of the S1D13504 11 Ground 12 Ground 13 Connected to DB8 of the S1D13504 14 Connected to DB9 of the S1D13504 15 Connected to DB10 of the S1D13504 16 Connected to DB11 of the S1D13504 17 Ground 18 Ground 19 Connected to DB12 of the S1D13504 20 Connected to DB13 of the S1D13504 21 Connected to DB14 of the S1D13504 22 Connected to DB15 of the S1D13504 ...

Page 361: ...round 11 Connected to AB8 of the S1D13504 12 Connected to AB9 of the S1D13504 13 Connected to AB10 of the S1D13504 14 Connected to AB11 of the S1D13504 15 Connected to AB12 of the S1D13504 16 Connected to AB13 of the S1D13504 17 Ground 18 Ground 19 Connected to AB14 of the S1D13504 20 Connected to AB14 of the S1D13504 21 Connected to AB16 of the S1D13504 22 Connected to AB17 of the S1D13504 23 Con...

Page 362: ...K Bus 1 MC68K Bus 2 Generic MPU AB 20 1 A 20 1 A 20 1 A 20 1 A 20 1 AB0 A0 LDS A0 A0 DB 15 0 D 15 0 D 15 0 D 31 16 D 15 0 WE1 WE1 UDS DS WE1 M R External Decode External Decode External Decode External Decode CS CSn External Decode External Decode External Decode BUSCLK CKIO CLK CLK BCLK BS BS AS AS Connect to IO VDD RD WR RD WR R W R W RD1 RD RD Connect to IO VDD SIZ1 RD0 WE0 WE0 Connect to IO VD...

Page 363: ... space On the S5U13504B00C the S1D13504 registers have been mapped to a start address of C00000h and the 2M byte display buffer has been mapped to a start address of E00000h 3 When using this board in a PC environment system memory must be limited to 12M bytes as more than this will conflict with the S1D13504 display buffer register addresses Note Due to backwards compatibility with the S5U13504B0...

Page 364: ...socket to eliminate conflicts resulting from two different outputs driving the same input Refer to Table 5 1 Host Bus Interface Pin Mapping on page 12 for connection details Note When using a 3 3V CPU Interface JP2 must be used to configure the S1D13504 IO VDD to 3 3V In this configuration all S1D13504 IO pins are configured for 3 3V output e g LCD inter face DRAM interface RAMDAC interface etc Al...

Page 365: ...supports 9 12 18 bit active matrix color TFT panels All the necessary signals can also be found on the 40 pin LCD connector J6 The interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems When supporting an 18 bit TFT panel the S1D13504 can display 64K of a possible 262K colors A maximum 16 of the possible 18 bits of LCD data is available from the ...

Page 366: ...13 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V Iout 45mA For ease of implementation such a power supply has been provided as an integral part of this design The signal VLCD can be adjusted by R37 to supply an output voltage from 14V to 23V and is enabled disabled by the S1D13504 control signal LCDPWR D...

Page 367: ...10 and Table 4 2 CPU BUS Connector H2 Pinout on page 11 for specific settings Note These headers only provide the CPU Bus interface signals from the S1D13504 When another host bus interface is selected through MD3 1 configuration appropriate external decode logic MUST be used to access the S1D13504 See the section Host Bus Interface Pin Mapping of the S1D13504 Hardware Functional Specification doc...

Page 368: ... 2 H1 H2 CON34A Male Header 0 1 2 x 17 Male Header 11 1 J5 PS 2 CONNECTOR Assman A HDF 15 A KG T or equivalent 12 1 J6 CON40A Shrouded Header 40 pin Dual row center key PTH 13 8 L1 L5 L7 L9 Ferrite Bead Fair rite 2743001111 PTH 14 1 L6 1uH Dale Inductor IM 4 1 0uH PTH 15 1 Q1 2N3906 PNP Signal Transistor TO 92 PTH 16 1 Q2 2N3903 NPN Signal Transistor TO 92 PTH 17 9 R10 R16 R18 R19 10K 10K Ohm 1206...

Page 369: ...0 15BCNT Texas Instrument PAL 24 pin DIP package socketed 32 1 U4 Osc 14 Fox 40 0MHz Oscillator or equiv 14 pin DIP socketed 33 1 U5 74LS125 14 pin SO 14 package 34 1 U6 BT481A BrookTree RAMDAC PLCC package 44 pin PLCC SMT part 35 1 U7 RD 0412 XENTECK Positive Power Supply 36 1 U8 EPN001 XENTECK Negative Power Supply 37 1 U9 LP2960AIN 3 3 National 3 3V Fixed Voltage Regulator N16G 16 PIN DIP packa...

Page 370: ...0 MA1 38 MA2 36 MA3 34 MA4 35 MA5 37 MA6 39 MA7 41 MD0 66 MD1 64 MD2 62 MD3 60 MD4 58 MD5 56 MD6 54 MD7 52 MD8 53 MD9 55 MD10 57 MD12 61 MD13 63 FPFRAME 69 FPLINE 70 FPSHIFT 73 FPDAT0 75 FPDAT1 76 FPDAT2 77 FPDAT3 78 FPDAT5 80 FPDAT6 81 FPDAT7 82 AB17 114 AB18 113 AB19 112 M R 5 CS 4 MA8 43 LCDPWR 71 VSS 15 VSS 32 VSS 68 VSS 96 VSS 109 MA9 GPIO3 45 VSS 87 VSS 74 AB20 111 MOD DRDY FPSHIFT2 72 FPDAT...

Page 371: ... VCC 3 3V U2 uPD4218 165LE 50 A0 17 A1 18 A2 19 A3 20 A4 23 A5 24 A6 25 A7 26 A8R A8 27 A9R A9 28 A10 NC 16 A11 NC 15 RAS 14 UCAS 30 LCAS 31 W 13 NC 11 NC 12 NC 32 OE 29 DQ0 2 DQ1 3 DQ2 4 DQ3 5 DQ4 7 DQ5 8 DQ6 9 DQ7 10 DQ8 33 DQ9 34 DQ10 35 DQ11 36 DQ12 38 DQ13 39 DQ14 40 DQ15 41 VCC 1 VCC 6 VCC 21 VSS 22 VSS 37 VSS 42 R9 15K R8 15K R7 15K R6 15K R5 15K R4 15K R3 15K R2 15K C1 01 C2 01 C3 01 S1 SW...

Page 372: ... SD6 3 SD5 4 SD4 5 SD3 6 SD2 7 SD1 8 SD0 9 IOCHRDY 10 AEN 11 SA19 12 SA18 13 SA17 14 SA16 15 SA15 16 SA14 17 SA13 18 SA12 19 SA11 20 SA10 21 SA9 22 SA8 23 SA7 24 SA6 25 SA5 26 SA4 27 SA3 28 SA2 29 SA1 30 SA0 31 J2 AT CON B GND 1 RESET 2 5V 3 IRQ9 4 5V 5 DRQ2 6 12V 7 OWS 8 12V 9 GND 10 SMEMW 11 SMEMR 12 IOW 13 IOR 14 DACK3 15 DRQ3 16 DACK1 17 DRQ1 18 REFRESH 19 CLK 20 IRQ7 21 IRQ6 22 IRQ5 23 IRQ4 2...

Page 373: ...ERRITE BEAD FAI R RITE 2743001111 FERR OXCUBE VK20019 4B PHILL IPS 431202036690 1 2 C19 10uF Tantulum J5 6 1 11 7 2 12 8 3 13 9 4 14 10 5 15 L3 1 2 L4 1 2 L5 1 2 R17 39 R20 39 R21 39 R22 39 R23 150 1 R24 150 1 R25 150 1 D4 1N4148 2 1 D5 2 1 D6 2 1 D1 1N4148 2 1 D2 2 1 D3 2 1 C15 01 C16 01 C17 01 C18 01 R18 10K R19 10K R28 39 R29 39 U6 BT481A D0 8 D1 9 D2 10 D3 11 D4 12 D5 13 D6 14 D7 15 RD 6 WR 16...

Page 374: ...PDAT2 FPDAT 0 7 VCC 12V 12V VCC VSS 3 3V JP3 HEADER 3 1 2 3 J6 CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 H1 HEADER 17X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 H2 HEADER 17X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 FPS...

Page 375: ...63V R34 1K R35 100K R36 100K Q2 2N3903 2 1 3 R30 470K R31 200K 1 3 2 R32 14K C23 10uF 63V Low ESR C24 10uF 63V Low ESR C26 56uF 35V C27 56uF 35V Low ESR C30 1uF C29 33uF Tantulum C22 56uF 35V R33 1K R37 100K 1 3 2 U7 RD 0412 VOUT_ADJ 1 DC_IN 2 REMOTE 3 GND 4 GND 5 GND 6 GND 7 GND 8 NC 9 GND 10 GND 11 DC_OUT 12 U8 EPN001 DC_OUT 1 DC_OUT 2 NC 3 GND 4 GND 5 VOUT_ADJ 6 NC 7 NC 8 NC 9 DC_IN 11 DC_IN 10...

Page 376: ...Page 26 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual X19A G 004 06 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 377: ...document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko E...

Page 378: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 THIS PAGE LEFT BLANK ...

Page 379: ...upport 14 4 2 Non PCI Host Interface Support 14 4 2 1 CPU Interface Pin Mapping 15 4 2 2 CPU Bus Connector Pin Mapping 16 4 3 LCD Support 18 4 3 1 LCD Interface Pin Mapping 19 4 3 2 Buffered LCD Connector 20 4 3 3 Adjustable LCD Panel Positive Power Supply VDDH 20 4 3 4 Manual Software Adjustable LCD Panel Negative Power Supply VLCD 20 4 4 Current Consumption Measurement 21 5 References 22 5 1 Doc...

Page 380: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 THIS PAGE LEFT BLANK ...

Page 381: ...S1 Location 9 Figure 3 2 Configuration Jumper JP1 Location 10 Figure 3 3 Configuration Jumper JP2 Location 11 Figure 3 4 Configuration Jumper JP3 Location 11 Figure 3 5 Configuration Jumper JP4 Location 12 Figure 3 6 Configuration Jumper JP5 Location 12 Figure 3 7 Configuration Jumper JP6 Location 13 Figure 3 8 Configuration Jumper JP7 Location 13 Figure 7 1 S5U13504B00C Rev 2 0 Evaluation Board S...

Page 382: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 THIS PAGE LEFT BLANK ...

Page 383: ...U13504B00C Rev 2 0 PCI Evalu ation Board The S5U13504B00C is designed as an evaluation platform for the S1D13504 Color LCD Controller chip This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at www erd epson com We appreciate your comments on our documentation Please contact us via emai...

Page 384: ...cting to a 3 3V host bus interface 5V host bus interface also possible with modifications to the board 1Mx16 EDO DRAM Configuration options Headers for S1D13504 current consumption measurements Adjustable positive LCD bias power supplies from 24V to 40V Adjustable negative LCD bias power supplies from 23V to 14V 4 8 bit 3 3V or 5V monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V color pa...

Page 385: ...here appropriate the S5U13504B00C hard wires some of these configuration inputs but in order to configure the S1D13504 for multiple host bus interfaces a five position DIP switch is required The following figure shows the location of DIP switch S1 on the S5U13504B00C board Figure 3 1 Configuration DIP Switch S1 Location The following DIP switch settings configure the S1D13504 Table 3 1 Configurati...

Page 386: ...PCI host system Note When used in a PCI environment JP1 must be set to the 1 2 position Figure 3 2 Configuration Jumper JP1 Location Table 3 2 Jumper Settings Jumper Function Position 1 2 Position 2 3 Jumper Off JP1 BUSCLK Selection BUSCLK from U2 oscillator BUSCLK from H2 header n a JP2 CLKI Selection CLKI from U3 oscillator CLKI is the same as BUSCLK n a JP3 CoreVDD current Normal operation n a ...

Page 387: ...ion 2 3 the CLKI source is the same as BUSCLK provided by the non PCI host system Figure 3 3 Configuration Jumper JP2 Location JP3 CoreVDD Current JP3 allows the mesurement of S1D13504 CoreVDD current consumption When the jumper is at position 1 2 the evaluation board is operating normally default setting When no jumper is installed CoreVDD current comsumption can be measured by connecting an ampm...

Page 388: ...ault setting When no jumper is installed IOVDD current comsumption can be measured by connecting an ampmeter to JP4 Figure 3 5 Configuration Jumper JP4 Location JP5 LCD Panel Voltage JP5 selects the voltage level to the LCD panel When the jumper is at position 1 2 the LCD panel voltage level is configured for 5 0V When the jumper is at position 2 3 the LCD panel voltage level is configured for 3 3...

Page 389: ... the LCDPWR signal is active low Figure 3 7 Configuration Jumper JP6 Location JP7 PCI FPGA Enable JP7 controls the PCI FPGA When no jumper is installed the PCI FPGA is enabled and the evaluation board may be used in a PCI environment default setting When the jumper is in position 1 2 the PCI FPGA is disabled and the evaluation board may be used with a non PCI host system Note Non PCI host system m...

Page 390: ...t The S5U13504B00C is specifically designed to support a standard PCI bus environment using the PCI Bridge Adapter FPGA However the S5U13504B00C can directly support many other Host Bus Interfaces When the FPGA is disabled using jumper JP7 headers H1 and H2 provide the necessary IO pins to interface to the Host Bus Interfaces listed in Table 4 1 CPU Interface Pin Mapping on page 15 Note The S5U135...

Page 391: ... Mapping S1D13504 Pin Names Generic Hitachi SH 3 Motorola MC68K Bus 1 Motorola MC68K Bus 2 AB20 A20 A20 A20 A20 AB19 A19 A19 A19 A19 AB18 A18 A18 A18 A18 AB17 A17 A17 A17 A17 AB 16 13 A 16 13 A 16 13 A 16 13 A 16 13 AB 12 1 A 12 1 A 12 1 A 12 1 A 12 1 AB0 A01 A01 LDS A0 DB 15 8 D 15 0 D 15 8 D 15 8 D 31 24 DB 7 0 D 7 0 D 7 0 D 7 0 D 23 16 WE1 WE1 WE1 UDS DS M R External Decode CS External Decode B...

Page 392: ...D13504 10 Connected to DB7 of the S1D13504 11 Ground 12 Ground 13 Connected to DB8 of the S1D13504 14 Connected to DB9 of the S1D13504 15 Connected to DB10 of the S1D13504 16 Connected to DB11 of the S1D13504 17 Ground 18 Ground 19 Connected to DB12 of the S1D13504 20 Connected to DB13 of the S1D13504 21 Connected to DB14 of the S1D13504 22 Connected to DB15 of the S1D13504 23 Connected to RESET o...

Page 393: ...d to AB8 of the S1D13504 12 Connected to AB9 of the S1D13504 13 Connected to AB10 of the S1D13504 14 Connected to AB11 of the S1D13504 15 Connected to AB12 of the S1D13504 16 Connected to AB13 of the S1D13504 17 Ground 18 Ground 19 Connected to AB14 of the S1D13504 20 Connected to AB15 of the S1D13504 21 Connected to AB16 of the S1D13504 22 Connected to AB17 of the S1D13504 23 Connected to AB18 of...

Page 394: ...TFT D TFD panels All necessary signals are provided on the 40 pin LCD connector J1 The interface signals are alternated with grounds on the cable to reduce cross talk and noise When supporting an 18 bit TFT D TFD panel the S1D13504 can display 64K of a possible 256K colors because only 16 of the 18 bits of LCD data are available from the S1D13504 For details refer to the S1D13504 Hardware Function...

Page 395: ...AT0 1 and 6 D0 LD0 D0 D0 LD0 LD0 R2 R3 R5 FPDAT1 3 D1 LD1 D1 D1 LD1 LD1 R1 R2 R4 FPDAT2 5 D2 LD2 D2 D2 LD2 LD2 R0 R1 R3 FPDAT3 7 D3 LD3 D3 D3 LD3 LD3 G2 G3 G5 FPDAT4 9 D0 D4 UD0 D0 D4 D4 UD0 UD0 G1 G2 G4 FPDAT5 11 D1 D5 UD1 D1 D5 D5 UD1 UD1 G0 G1 G3 FPDAT6 13 and 4 D2 D6 UD2 D2 D6 D6 UD2 UD2 B2 B3 B5 FPDAT7 15 D3 D7 UD3 D3 D7 D7 UD3 UD3 B1 B2 B4 FPDAT8 17 LD4 B0 B1 B3 FPDAT9 19 LD5 R0 R2 FPDAT10 2...

Page 396: ... S1D13504 inverted by U6 to control the MAX754 as shown in the following table Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel 4 3 4 Manual Software Adjustable LCD Panel Negative Power Supply VLCD Most passive monochrome LCD panels require a negative bias voltage between 14V and 24V The S5U13504B00C use...

Page 397: ...3504 Issue Date 2002 12 02 X19A G 014 01 4 4 Current Consumption Measurement The evaluation board has 2 headers JP3 and JP4 which allow the independent measurement of S1D13504 CoreVDD and IOVDD current consumption To measure the current remove the appropriate jumper and connect an ammeter to the corresponding header pins ...

Page 398: ...ssue Date 2002 12 02 5 References 5 1 Documents Epson Research and Development Inc S1D13504 Hardware Functional Specification document number X19A A 001 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples document number X19A G 002 xx 5 2 Document Sources Epson Research and Development Website http www erd epson com ...

Page 399: ...nic ECG EEV FK1J100P 7 2 D1 D2 SOD123 1N5819HW Diodes Inc 1N5819HW 7 8 2 H1 H2 HEADER 17x2 HEADER 17X2 Molex 10 88 1341 or equivalent 9 4 JP1 JP2 JP5 JP6 HEADER 3 HEADER 3x1 0 1 pitch 10 3 JP3 JP4 JP7 HEADER 2 HEADER 2x1 0 1 pitch 11 1 J1 HEADER 20x2 CON40A Amp103308 8 or equivalent 12 2 L1 L2 INDPM105S 47uH JW Miller Inc PM105S 470M 13 1 Q1 SOT23 MMBT3906 Diodes Inc MMBT3906 7 14 1 Q2 SOT223 NDT3...

Page 400: ... socket 14 pin 36 1 U3 DIP14 25MHz Epson SG8002DB 25MHz 37 1 U4 DDPAK 2 LT1117CM 3 3 Linear Technologies LT1117CM 3 3 38 1 U5 SOJ42 DRAM 1Mx16 SOJ Micron MT4LC1M16E5DJS 5 or ISSI IS41lv16100 39 1 U6 SC70 5 INVERTER SINGLE NC7S04 Fairchild Semiconductor NC7S04P5 40 3 U7 U8 U9 SO20W 74AHC244 TI 74AHC244 41 1 U10 SO16N MAX754CSE Maxim Integrated Products MAX754CSE 42 1 U11 SO8N MAX749CSA Maxim Integr...

Page 401: ...3V 3 3V 5V C3 0 1uF R3 100K 5 JP4 IO CURRENT 1 2 1 2 C5 0 1uF C9 0 1uF JP1 BUSCLK 1 2 3 C4 0 1uF U1 13504F0A 3 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 40 38 36 34 35 37 39 41 66 64 62 60 58 56 54 52 53 55 57 61 63 69 70 73 75 76 77 78 80 81 82 114 113 112 5 4 43 71 15 32 68 96 109 45 87 74 111 72 92 93 94 95 51 104 42 59 44 65 67 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 402: ...stors 1 0 S5U13504B00C PCI Bus 13504F0A Chip 2 5 Wednesday August 28 2002 B Epson Research Development Inc Title Size Document Number Rev Date Sheet of MA 9 0 MD 15 0 MD9 MD7 MD8 MD6 MD14 MD12 MD5 MD4 MD0 MD10 MD3 MA5 MD15 MA8 MD13 MD11 MD2 MD1 MA6 MA4 MA2 MA3 MA1 MA7 MA0 MA9 MD9 MD5 MD6 MD10 MD2 MD4 MD0 MD1 MD 15 0 MD 15 0 1 MA 9 0 1 RAS 1 UCAS 1 LCAS 1 WE 1 MD 15 0 1 IOVDD IOVDD S1 S1D13504 Conf...

Page 403: ...PDAT 15 0 1 LCDPOWER LCDPOWER 12V VDDH VLCD LCDVCC LCDVCC LCDVCC LCDVCC IOVDD 5V 3 3V LCDVCC IOVDD VDDH 5V 5V 5V VLCD 5V 5V C23 0 1uF L1 47uH C24 22uF 10V T 1 2 R12 301 1 Q4 FZT792A 1 2 3 4 C22 0 1uF R15 82K JP6 LCD PWR SELECT 1 2 3 RV2 500k POT 1 3 2 C19 0 1uF D1 1N5819HW 1 2 R20 1 2M J1 CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 3...

Page 404: ...5V 12V 5V 5V 12V 12V 5V 5V 5V C43 33uF 20V 10 PCIB1 PCI B 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 12V TCK GND TDO 5V 5V INTB INTD PRSNT 1 RESERVED PRSNT 2 RESERVED GND CLK GND REQ VI O AD31 AD29 GND AD27 AD25 3 3V C BE3 AD23 GND AD21 AD19 3 3V AD17 C BE2 GND IRDY 3 3V DEVSEL...

Page 405: ...8 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 IO1 I...

Page 406: ...esearch and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 8 Board Layout Figure 8 1 S5U13504B00C Rev 2 0 Evaluation Board Layout ...

Page 407: ...r Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH ...

Page 408: ...Page 32 Epson Research and Development Vancouver Design Center S1D13504 S5U13504B00C Rev 2 0 PCI Evaluation Board User Manual X19A G 014 01 Issue Date 2002 12 02 THIS PAGE LEFT BLANK ...

Page 409: ...d use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark...

Page 410: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 411: ...nnection to the Philips PR31500 PR31700 11 4 1 Hardware Description 11 4 2 Memory Mapping and Aliasing 12 4 3 S1D13504 Configuration 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description Using One IT8368E 14 5 2 Hardware Description Using Two IT8368E s 17 5 3 IT8368E Configuration 18 5 4 Memory Mapping and Aliasing 19 5 5 S1D13504 Configuration 20 6 Software 21 7 Referenc...

Page 412: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 413: ...rect Connection 13 Table 5 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping 19 Table 5 2 PR31500 PR31700 to PC Card Slots Address Remapping using the IT8368E 19 Table 5 3 S1D13504 Configuration using the IT8368E 20 Table 5 4 S1D13504 Host Bus Selection using the IT8368E 20 List of Figures Figure 4 1 Typical Implementation of S1D13504 to PR31500 PR31700 Direct Connection 11 Figu...

Page 414: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 415: ...olor Graphics LCD CRT Controller and the Philips MIPS PR31500 PR31700 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any development We...

Page 416: ...nterface that the S1D13504 connects to the PR31500 PR31700 processor The S1D13504 can be successfully interfaced using one of three configurations Direct connection to PR31500 PR31700 see Section 4 Direct Connection to the Philips PR31500 PR31700 on page 11 System design using one ITE8368E PC Card GPIO buffer chip see Section 5 1 Hard ware Description Using One IT8368E on page 14 System design usi...

Page 417: ...rface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is imp...

Page 418: ...bles for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals mus...

Page 419: ...eneric MPU host bus interface capability of the S1D13504 The following diagram demonstrates a typical implementation of the PR31500 PR31700 to S1D13504 interface Figure 4 1 Typical Implementation of S1D13504 to PR31500 PR31700 Direct Connection Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping RD1 RD0 DB 7 0 WAIT BUSCLK S1D13504 RESET AB 20 13 RD D 31 24 CARD1WAIT A 12 ...

Page 420: ...om the PR31500 PR31700 to the M R input of the S1D13504 Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E see Section 5 System Design Using the IT8368E PC Card Buffer on page 14 All other addresses are ignored The S1D13504 address ranges as seen by the PR31500 PR31700 on the PC Card slot 1 memory space are as follows 6400 0000h S1D13504 r...

Page 421: ...04 Configuration for Direct Connection S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 See Host Bus Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT signal is active high WAIT signal is active low required configuration for direct connection with...

Page 422: ...TE IT8368E has been specifically designed to support EPSON LCD CRT controllers The IT8368E provides eleven Multi Function IO pins MFIO Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface The Philips PR31500 PR31700 processor only provides addresses A 12 0 therefore devices that occupy more address space must u...

Page 423: ...AIT CARDxWAIT M R RESET Latch ALE AB 20 13 A23 PR31500 PR31700 D 23 16 DB 15 8 DCLKOUT Chip Select Logic Notes The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number ENDIAN System RESET BUSCLK Oscillator or pull up VDD BS IO VDD Clock divider...

Page 424: ...with respect to the S1D13504 bus clock This gives the system designer full flexibility in choosing the appropriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired pixel and frame rates power budget part count maximum S1D13504 clock frequencies The S1D13504 also has internal c...

Page 425: ...LHA22 MFIO9 LHA21 MFIO8 LHA20 MFIO7 LHA19 MFIO6 WAIT CARDxWAIT M R RESET AB 20 13 LHA23 PR31500 PR31700 D 23 16 DB 15 8 DCLKOUT Notes The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx IT8368E Chip Select Logic ...

Page 426: ...1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 5 3 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E or the first in a two IT8368E implementation must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the S1D13504 host bus int...

Page 427: ...ls of the Attribute IO address re allocation by the IT8368E Table 5 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping TX3912 Address Size Function CARDnIOEN 0 Function CARDnIOEN 1 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 IO 6400 0000h 64M byte Card 1 Memory 6400 0000h 64M byte Card 2 Memory Table 5 2 PR31500 PR31700 to PC Card Sl...

Page 428: ... 5 3 S1D13504 Configuration using the IT8368E S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 See Host Bus Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT signal is active high WAIT signal is active low required configuration for connection usin...

Page 429: ... is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales s...

Page 430: ...nc S1D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 7 2 Document Sources Philips Electronics Website http www us2 ...

Page 431: ...o 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de North America Epson Ele...

Page 432: ...Page 24 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Philips MIPS PR31500 PR31700 Processor X19A G 005 09 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 433: ...but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corp...

Page 434: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Power Consumption X19A G 006 04 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 435: ...umption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There are two power save modes in the...

Page 436: ...ired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13504 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility Table 1 1 S1D13504 Total Power Consumption Test Condition Core VDD 3 3V IO VDD 5 0V ISA Bus 8MHz Gray Shades Colors Total...

Page 437: ...his document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Sei...

Page 438: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 439: ... 8 2 1 2 LCD Memory Access Cycles 9 3 S1D13504 Host Bus Interface 10 3 1 Generic MPU Host Bus Interface Pin Mapping 10 3 2 Generic MPU Host Bus Interface Signals 11 4 VR4102 to S1D13504 Interface 12 4 1 Hardware Description 12 4 2 S1D13504 Hardware Configuration 13 4 3 NEC VR4102 Configuration 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 7 1 EPSO...

Page 440: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 441: ...X19A G 007 08 List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 13 Table 4 2 Host Bus Interface Selection 13 Table 4 2 NEC S1D13504 Truth Table 14 List of Figures Figure 2 1 NEC VR4102 Read Write Cycles 9 Figure 4 1 Typical Implementation of VR4102 to S1D13504 Interface 12 ...

Page 442: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 443: ...designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development ...

Page 444: ...stablish interface requirements 2 1 1 Overview The NEC VR4102 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices using its ADD and DAT buses which can be dynamically size...

Page 445: ...DCS is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB is driven low for 16 bit transfers and high for 8 bit transfers The following figure illustrates typical NEC VR4102 memory read and write cycles to the LCD controller interface Figure 2 1 NEC VR4102 Read Write Cy...

Page 446: ...s assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to re...

Page 447: ...r the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be ge...

Page 448: ...mplementation of the VR4102 to S1D13504 interface Figure 4 1 Typical Implementation of VR4102 to S1D13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping WE1 WE0 DB 15 0 WAIT RD1 RD0 BUSCLK S1D13504 CS M R RESET AB 20 0 A0 A0 A21 SHB WR DAT 15 0 LCDCS RD BUSCLK LCDRDY ADD 25 0 NEC VR4102 Pull up Notes The propagation delay of the Read write Decode Logic show...

Page 449: ...nterface Table 4 1 Summary of Power On Reset Options S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active low 0 insert wait state con...

Page 450: ...ress line A21 is used to select between the S1D13504 display buffer and internal register set The VR4102 uses a read write and system high byte enable to interface to an external LCD controller The S1D13504 uses low and high byte read and write strobes and therefore minimal glue logic is necessary Table 4 2 NEC S1D13504 Truth Table NEC Signals Cycle S1D13504 Signals SHB RD WR A0 1 0 1 0 8 bit even...

Page 451: ...ilable for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales support ...

Page 452: ...0 Epson Research and Development Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources NEC Electronics Website http www necel co...

Page 453: ...ax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel ...

Page 454: ...Page 18 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the NEC VR4102 Microprocessor X19A G 007 08 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 455: ...and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered tradema...

Page 456: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 457: ... 2 Chip Select Module 8 3 S1D13504 Host Bus Interface 9 3 1 Generic MPU Host Bus Interface Pin Mapping 9 3 2 Generic MPU Host Bus Interface Signals 10 4 MC68328 To S1D13504 Interface 11 4 1 Hardware Description 11 4 2 S1D13504 Hardware Configuration 13 4 3 MC68328 Chip Select Configuration 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 7 1 EPSON LC...

Page 458: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 459: ...f Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping 9 Table 4 1 Summary of Power On Reset Options 13 Table 4 2 S1D13504 Host Bus Selection 13 Table 4 3 Memory Configuration 14 List of Figures Figure 4 1 Block Diagram of MC68328 to S1D13504 Interface MC68000 Bus 1 Interface Mode 11 Figure 4 2 Block Diagram of MC68328 to S1D13504 Interface Generic Interface Mode 12 ...

Page 460: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 461: ... refresh memory the S1D13504 can reduce system power consumption improve image quality and increase system performance as compared to the Dragonball s on chip LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development website at ...

Page 462: ...tly to the S1D13504 with no glue logic However several of the 68000 bus control signals are multiplexed with I O and interrupt signals on the 68328 and in many applications it may be desirable to make these pins available for these alternate functions This requirement may be accommodated through use of the Generic Bus interface mode on the S1D13504 2 2 Chip Select Module The 68328 can generate up ...

Page 463: ...t the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to remember to clear this bit before proceeding with debug...

Page 464: ...nables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals m...

Page 465: ...htforward implementation of the MC68000 Bus 1 interface mode as described in the S1D13504 Hardware Functional Specification document number X19A A 002 xx Following are the electrical connections required for this interface Figure 4 1 Block Diagram of MC68328 to S1D13504 Interface MC68000 Bus 1 Interface Mode MC68328 S1D13504 A 20 1 D 15 0 DTACK UDS LDS R W CLK0 AB 20 1 SD 15 0 CS WAIT WE1 AB0 RD1 ...

Page 466: ... time of the WAIT TA signal when terminating the bus cycle Figure 4 2 Block Diagram of MC68328 to S1D13504 Interface Generic Interface Mode The S1D13504 requires a 2M byte address space for the display buffer plus a few more locations to access its internal registers To accommodate this relatively large block size it is preferable to use one of the chip selects from groups A or B but this is not r...

Page 467: ...us Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 Wait signal is active high Wait signal is active low MD6 See Memory Configuration table below See Memory Configuration table below MD7 MD8 Configure DACRD BLANK DACP0 DACWR DACRS0 DACRS1 HRTC VRTC as GPIO4 11 Configure DACRD BLANK DACP0 DACWR DACRS0 DACRS1 HRTC VRTC as DAC CRT outputs MD9 Configure...

Page 468: ...is used The S1D13504 control registers are mapped into the bottom half of this address block while the display buffer is mapped into the top half The chip select should have its RO Read Only bit set to 0 and the WAIT field Wait states should be set to 111 to allow the S1D13504 to terminate bus cycles externally Table 4 3 Memory Configuration MD7 MD6 Option Memory Selection 0 0 1 Symmetrical 256K x...

Page 469: ...de is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales...

Page 470: ...68328UM AD Epson Research and Development Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx 6 2 Document Sources Motorola Inc Motorola Literature...

Page 471: ... jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2...

Page 472: ...Page 18 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MC68328 Dragonball Microprocessor X19A G 013 03 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 473: ...ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epso...

Page 474: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 475: ... Memory Access Cycles 8 3 S1D13504 Host Bus Interface 10 3 1 Generic MPU Host Bus Interface Pin Mapping 10 3 2 Generic MPU Host Bus Interface Signals 11 4 PC Card to S1D13504 Interface 12 4 1 Hardware Description 12 4 2 S1D13504 Hardware Configuration 13 4 3 PAL Equations 14 4 4 Register Memory Mapping 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17...

Page 476: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 477: ...X19A G 009 05 List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Options 13 Table 4 2 Host Bus Interface Selection 13 List of Figures Figure 2 1 PC Card Read Cycle 9 Figure 2 2 PC Card Write Cycle 9 Figure 4 1 Typical Implementation of PC Card to S1D13504 Interface 12 ...

Page 478: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 479: ...lor Graphics LCD CRT Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comm...

Page 480: ...is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 16 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 c...

Page 481: ... lengthened by driving WAIT low for the time needed to complete the cycle The figure below illustrates a typical memory read cycle on the PC Card bus Figure 2 1 PC Card Read Cycle The figure below illustrates a typical memory write cycle on the PC Card bus Figure 2 2 PC Card Write Cycle A 25 0 CE1 OE WAIT ADDRESS VALID DATA VALID Hi Z Hi Z D 15 0 REG CE2 Transfer Start Transfer Complete A 25 0 CE1...

Page 482: ...ir selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to cle...

Page 483: ...r the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be ge...

Page 484: ...n address line so that it can be controlled using system address A21 BS bus start is not used and should be tied low connected to GND The PC Card interface does not provide a bus clock so one must be supplied for the S1D13504 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI The following diagram shows a typical implement...

Page 485: ...s important to the PC Card interface Table 4 1 Summary of Power On Reset Options S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active...

Page 486: ...MBINATORIAL S1D13504 reset PIN 10 gnd supply PIN 20 vcc supply EQUATIONS rd0 oe ce1 pcreg pcreg means disable in attribute mode rd1 oe ce2 pcreg pcreg means disable in attribute mode we0 we ce1 pcreg pcreg means disable in attribute mode we1 we ce2 pcreg pcreg means disable in attribute mode cs rd0 rd1 we0 we1 reset breset inversion appears in pin declaration section 4 4 Register Memory Mapping Th...

Page 487: ... the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and Windows CE v2 0 display drivers are available from yo...

Page 488: ...elopment Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx 6 2 Document Sources PC Card Website http www pc card com Epson Electronics America We...

Page 489: ...27 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electroni...

Page 490: ...Page 18 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the PC Card Bus X19A G 009 05 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 491: ...e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of ...

Page 492: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 493: ...e GPCM 11 2 3 2 User Programmable Machine UPM 12 3 S1D13504 Host Bus Interface 13 3 1 Generic MPU Host Bus Interface Pin Mapping 13 3 2 Generic MPU Host Bus Interface Signals 14 4 MPC821 to S1D13504 Interface 15 4 1 Hardware Description 15 4 2 Hardware Connections 16 4 3 S1D13504 Hardware Configuration 18 4 4 Register Memory Mapping 19 4 5 MPC821 Chip Select Configuration 19 4 6 Test Software 20 4...

Page 494: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 495: ...Table 3 1 Generic MPU Host Bus Interface Pin Mapping 13 Table 4 1 List of Connections from MPC821ADS to S1D13504 16 Table 4 2 Summary of Power On Reset Options 18 Table 4 2 Host Bus Interface Selection 18 List of Figures Figure 2 1 Power PC Memory Read Cycle 9 Figure 2 2 Power PC Memory Write Cycle 10 Figure 4 1 Typical Implementation of MPC821 to S1D13504 Interface 15 ...

Page 496: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MPC821 Microprocessor X19A G 010 06 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 497: ...olor Graphics LCD CRT Controller and the Motorola MPC821 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreci...

Page 498: ...ming generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in ...

Page 499: ...gh for read cycles and low for write cycles AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The min...

Page 500: ... 8 bit transfers data lines D0 through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 1 3 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions ...

Page 501: ... memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The AC...

Page 502: ...rol address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application ...

Page 503: ...elected by the S1D13504 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design ...

Page 504: ... by the host CPU WE0 and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 WAIT is a signal output from the S1D13504 that indicates the host CPU must ...

Page 505: ...sed in this implementation and must be connected to IO VDD The following diagram shows a typical implementation of the MPC821 to S1D13504 interface Figure 4 1 Typical Implementation of MPC821 to S1D13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping MPC821 S1D13504 A 11 31 D 0 15 CS4 TA WE0 WE1 OE SYSCLK AB 20 0 DB 15 0 CS WAIT WE1 WE0 RD1 RD0 BUSCLK RESET...

Page 506: ...tor and Pin Name S1D13504 Signal Name Vcc P6 A1 P6 B1 Vcc A10 P6 C23 M R A11 P6 A22 AB20 A12 P6 B22 AB19 A13 P6 C21 AB18 A14 P6 C20 AB17 A15 P6 D20 AB16 A16 P6 B24 AB15 A17 P6 C24 AB14 A18 P6 D23 AB13 A19 P6 D22 AB12 A20 P6 D19 AB11 A21 P6 A19 AB10 A22 P6 D28 AB9 A23 P6 A28 AB8 A24 P6 C27 AB7 A25 P6 A26 AB6 A26 P6 C26 AB5 A27 P6 A25 AB4 A28 P6 D26 AB3 A29 P6 B25 AB2 A30 P6 B19 AB1 A31 P6 D17 AB0 D...

Page 507: ...ficant address bit is A0 the next is A1 A2 etc D12 P12 B14 DB3 D13 P12 D14 DB2 D14 P12 B13 DB1 D15 P12 C13 DB0 SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS TA P6 B6 WAIT WE0 P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD1 RD0 Gnd P12 A1 P12 B1 P12 A2 P12 B2 P12 A3 P12 B3 P12 A4 P12 B4 P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Vss Table 4 1 List of Connections from MPC821ADS to S1D13504 Continued MPC821 ...

Page 508: ... 2 Summary of Power On Reset Options S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 For host bus interface selection see Table 4 2 Host Bus Interface Selection MD2 MD3 MD4 Little Endian Big Endian MD5 Wait signal is active high Wait signal is active low MD9 Reserved Configure SUSPEND pin as Hardwar...

Page 509: ...he base address register BR4 BA 0 16 0000 0000 0100 0000 0 set starting address of S1D13504 to 40 0000h AT 0 2 0 ignore address type bits PS 0 1 1 0 memory port size is 16 bit PARE 0 disable parity checking WP 0 disable write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the op...

Page 510: ...BUG the debugger provided with the ADS board It was run on the ADS and a logic analyzer was used to verify operation of the interface hardware 4 6 1 Source Code BR4 equ 120 CS4 base register OR4 equ 124 CS4 option register MemStart equ 40 upper word of S1D13504 start address DisableReg equ 1b address of S1D13504 Disable Register RevCodeReg equ 0 address of Revision Code Register Start mfspr r1 IMM...

Page 511: ...have been added for clarity Note It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled the MMU must be setup so the S1D13504 memory block is tagged as non cacheable This ensures that accesses to the S1D13504 will occur in proper order and the MPC821 will not attempt to cache any data read from or written to the S1D13504...

Page 512: ...available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales suppo...

Page 513: ...nt Inc S1D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources Motorola Inc Motorola Literature Dist...

Page 514: ...g Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 htt...

Page 515: ...nd use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademar...

Page 516: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 517: ... 8 2 1 3 Burst Cycles 10 2 2 Chip Select Module 10 3 S1D13504 Bus Interface 11 3 1 Generic MPU Host Bus Interface Pin Mapping 11 3 2 Generic MPU Host Bus Interface Signals 12 4 MCF5307 To S1D13504 Interface 13 4 1 Hardware Connections 13 4 2 S1D13504 Hardware Configuration 14 4 3 Memory Register Mapping 15 4 4 MCF5307 Chip Select Configuration 15 5 Software 16 6 References 17 6 1 Documents 17 6 2 ...

Page 518: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 519: ...01 02 02 X19A G 011 07 List of Tables Table 3 1 Generic MPU Host Bus Interface Pin Mapping 11 Table 4 1 S1D13504 Configuration Settings 14 Table 4 2 S1D13504 Host Bus Selection 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle 9 Figure 2 2 MCF5307 Memory Write Cycle 9 Figure 4 1 Typical Implementation of MCF5307 to S1D13504 Interface 13 ...

Page 520: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A G 011 07 Issue Date 01 02 02 THIS PAGE LEFT BLANK ...

Page 521: ...e microprocessor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for t...

Page 522: ... separate IO space in the MCF5307 architecture The bus can support two types of cycle normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions The bus master initiates a data transfer by placing the memory address on address lines A31 through A0 and...

Page 523: ...CF5307 system bus Figure 2 1 MCF5307 Memory Read Cycle The following figure illustrates a typical memory read cycle on the MCF5307 system bus Figure 2 2 MCF5307 Memory Write Cycle A 31 0 D 31 0 SIZ 1 0 TT 1 0 TS TA BCLK0 Wait States Transfer Start Transfer Next Transfer Sampled when TA low R W Complete Starts TIP A 31 0 D 31 0 SIZ 1 0 TT 1 0 TS TA BCLK0 Wait States Transfer Start R W Valid Transfe...

Page 524: ...dependent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects 0 and 1 can be programmed independently to respond to any base address and block size Chip s...

Page 525: ... on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give...

Page 526: ...ly tied to an address line on CPUs with separate IO spaces this pin is typically driven by control logic from the CPU WE0 and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 RD and RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data fr...

Page 527: ... the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and should be tied low connected GND The following diagram shows a typical implementation of the MCF5307 to S1D13504 interface Figure 4 1 Typical Implementation of MCF5307 to S1D13504 Interface Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping MCF5307 S1D13504 A 20 0 D 31 ...

Page 528: ...lue on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 See Host Bus Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 Wait signal is active high Wait signal is active low MD9 Configure SUSPEND pin as GPO output Configure SUSPEND pin as Hardware Suspend Enable required settings f...

Page 529: ...D13504 CS4 selects a 2M byte address space for the S1D13504 control registers while CS5 selects the 2M byte display buffer The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 WP 0 disable write protect AM 0 enable alternate bus master access to the S1D13504 C I 1 disable CPU space access...

Page 530: ...ilable for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and Windows CE v2 0 display drivers are av...

Page 531: ...on Research and Development Inc S1D13504 Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S1U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 6 2 Document Sources Motorola Inc Motorola Literature Distribution ...

Page 532: ...7 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 ...

Page 533: ... this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of S...

Page 534: ...Page 2 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 535: ...tion to the Toshiba TX3912 11 4 1 Hardware Description 11 4 2 Memory Mapping and Aliasing 12 4 3 S1D13504 Hardware Configuration 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description Using One IT8368E 14 5 2 Hardware Description Using Two IT8368E s 16 5 3 IT8368E Configuration 18 5 4 Memory Mapping and Aliasing 19 5 5 S1D13504 Configuration 20 6 Software 21 7 References 2...

Page 536: ...Page 4 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 537: ...s Selection for Direct Connection 13 Table 5 1 TX3912 to Unbuffered PC Card Slots System Address Mapping 19 Table 5 2 TX3912 to PC Card Slots Address Remapping using the IT8368E 19 Table 5 3 S1D13504 Configuration using the IT8368E 20 Table 5 4 S1D13504 Host Bus Selection using the IT8368E 20 List of Figures Figure 4 1 Typical Implementation of TX3912 to S1D13504 Direct Connection 11 Figure 5 1 S1...

Page 538: ...Page 6 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

Page 539: ...olor Graphics LCD CRT Controller and the Toshiba TX3912 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We apprecia...

Page 540: ... interface that the S1D13504 connects to the TX3912 processor The S1D13504 can be successfully interfaced using one of three configurations Direct connection to TX3912 see Section 4 Direct Connection to the Toshiba TX3912 on page 11 System design using one ITE8368E PC Card GPIO buffer chip see Section 5 1 Hard ware Description Using One IT8368E on page 14 System design using two ITE8368E PC Card G...

Page 541: ...nals assume their selected configuration Note After reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh will be set to logic 1 meaning that the S1D13504 will not respond to any host accesses until a write to REG 1Bh clears this bit to 0 When debugging a new hardware design this can sometimes give the appearance that the interface is not work ing so it is important to...

Page 542: ...for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13504 These signals must be generated by external hardware based on the control outputs from the host CPU RD RD0 and RD WR RD1 are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13504 These signals must be ...

Page 543: ...U host bus interface capability of the S1D13504 The following diagram demonstrates a typical implementation of the TX3912 to S1D13504 interface Figure 4 1 Typical Implementation of TX3912 to S1D13504 Direct Connection Note For pin mapping see Table 3 1 Generic MPU Host Bus Interface Pin Mapping RD1 RD0 DB 7 0 WAIT BUSCLK S1D13504 RESET AB 20 13 RD D 31 24 CARD1WAIT A 12 0 TX3912 15K pull up CLKI O...

Page 544: ...lexed from the TX3912 to the M R input of the S1D13504 Using A23 makes this implemen tation software compatible with the two implementations that use the ITE IT8368E see Section 5 System Design Using the IT8368E PC Card Buffer on page 14 All other addresses are ignored The S1D13504 address ranges as seen by the TX3912 on the PC Card slot 1 memory space are as follows 6400 0000h S1D13504 registers ...

Page 545: ... 1 S1D13504 Configuration for Direct Connection S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 See Host Bus Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT signal is active high WAIT signal is active low required configuration for direct connec...

Page 546: ...8368E has been specifically designed to support EPSON CRT LCD controllers The IT8368E provides eleven Multi Function IO pins MFIO Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface The Toshiba TX3912 processor only provides addresses A 12 0 therefore devices that occupy more address space must use an external...

Page 547: ...CARDxWAIT M R RESET Latch ALE AB 20 13 A23 TX3912 D 23 16 DB 15 8 DCLKOUT Chip Select Logic Notes The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx ENDIAN System RESET BUSCLK Oscillator or pull up VDD BS IO VDD Clock divide...

Page 548: ...opriate source or sources for CLKI and BUSCLK Deciding whether both clocks should be the same and whether to use DCLKOUT divided as the clock source should be based on the desired pixel and frame rates power budget part count maximum S1D13504 clock frequencies The S1D13504 also has internal clock dividers providing additional flexibility 5 2 Hardware Description Using Two IT8368E s The following i...

Page 549: ...ESET AB 20 13 LHA23 TX3912 D 23 16 DB 15 8 DCLKOUT Notes The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing for details refer to the S1D13504 Hardware Functional Specification document number X19A A 002 xx IT8368E Chip Select Logic LHA 20 13 System RESET ENDIAN BUSCLK Oscillator or pull up VDD BS IO VDD Cloc...

Page 550: ... has internal clock dividers providing additional flexibility 5 3 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E or the first in a two IT8368E implementation must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the S1D13504 host bus interface and a 16M byte portion of the system...

Page 551: ...by the IT8368E Table 5 1 TX3912 to Unbuffered PC Card Slots System Address Mapping TX3912 Address Size Function CARDnIOEN 0 Function CARDnIOEN 1 0800 0000h 64Mb Card 1 Attribute Card 1 IO 0C00 0000h 64Mb Card 2 Attribute Card 2 IO 6400 0000h 64Mb Card 1 Memory 6400 0000h 64Mb Card 2 Memory Table 5 2 TX3912 to PC Card Slots Address Remapping using the IT8368E IT8368E Uses PC Card Slot TX3912 Addres...

Page 552: ... S1D13504 Configuration using the IT8368E S1D13504 Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MD0 8 bit host bus interface 16 bit host bus interface MD1 See Host Bus Selection table below See Host Bus Selection table below MD2 MD3 MD4 Little Endian Big Endian MD5 WAIT signal is active high WAIT signal is active low required configuration for connection using IT...

Page 553: ...vailable for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13504CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13504 test utilities and display drivers are available from your sales suppor...

Page 554: ...D13504 Color Graphics LCD CRT Controller Hardware Functional Specification Document Number X19A A 002 xx Epson Research and Development Inc S5U13504B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 004 xx Epson Research and Development Inc S1D13504 Programming Notes and Examples Document Number X19A G 002 xx 7 2 Document Sources Toshiba America Electrical Components Website ...

Page 555: ...pson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epso...

Page 556: ...Page 24 Epson Research and Development Vancouver Design Center S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor X19A G 012 05 Issue Date 01 10 26 THIS PAGE LEFT BLANK ...

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