S1R72104 Technical Manual
22
EPSON
Rev.1.1
Select_WithATN_Command(0AH)
Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase.
This command is valid in either disconnected or connected condition. It causes a command error if issued
when any other command is under execution.
CPU sets the message byte number in NON-DMA data-size register before issuing this command.
Then, the CPU write message data in FIFO. After transferring the message, it sets the command byte number
in NON-DMA data-size register, writing the command data in FIFO.
The IC acts as follows:
Waits for busfree.
After detecting busfree, enters arbitration.
If it wins arbitration, it asserts XSSEL and ID bit, entering the selection phase. Asserts XSATN at this time.
After selection, it checks message-out at the timing when XSREQ is asserted, transferring messages in FIFO.
Negates XSATN after asserting XSREQ and before asserting XSACK at the last byte of the messages.
After transferring all the messages, it checks the command phase, detects data accumulated in FIFO, and
transfers the command data in FIFO according to the byte number set anew.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After that, the IC enters Initiator mode.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
Select_WithoutATN_Command(0BH)
Executes selection keeping SCSI ATN negated, and then executes the command phase.
This command is valid in either disconnected or connected condition. It causes a command error if issued
when any other command is under execution.
CPU issues this command after setting the command byte number in NON_DMA data-size register.
The command data is written in FIFO.
The IC acts as follows:
Waits for busfree.
Enters arbitration after detecting busfree.
If it wins arbitration, it asserts XSSEL and ID bit, entering the selection phase.
After selection, it checks the command phase at the timing when XSREQ is asserted, transferring command
data from FIFO.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After those steps are over, the IC enters Initiator mode.
Wait_Select_Command(0CH)
Waits for the selection phase, and executes the command phase after selection.
Valid only when it is not connected.
If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other
command is under execution then, it continues execution.
If this command is issued, set STATN(bit5) of SCSIMODE register, and clear it when the command is over.
After the command was issued, the IC acts as follows:
1
Waits for selection phase.
2
If selected, checks XSATN. If it is not asserted, the IC acts as mentioned in
5
.
If it is asserted, the IC sets the message-out phase, receiving a message.
3
If the message received is not "Identify", the IC acts as mentioned in
6
. (CPU checks the message in FIFO
and responds to it.)
4
If XSATN remains asserted after 1-byte message ("Identify") was received, the IC ends its operation by
setting SATN bit of SCSIINT1 register and causing interruption.
If XSATN is negated,
5
The command phase is set to receive a command.
The IC distinguishes the command groups, deciding the number of bytes received automatically.
6
It sets GOOD bit of MAININT register, causing interruption.
