S1R72104 Technical Manual
Rev.1.1
EPSON
27
Message_In (18H)
Executes the message-in phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If it is issued in the disconnected condition,
It sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
CPU sets the message bytes to be sent in NON-DMA data-size register, and issues this command. It writes
messages to be transferred in FIFO.
The IC sets the message phase, and sends the data bytes set in FIFO.
It suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that,
It sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
In Initiator mode
CPU sets the message bytes to be received in NON-DMA data-size register before issuing this command.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Enters the byte size of message set into FIFO after checking the message-in phase at the timing when REQ is
asserted. REQ-ACK hand-shake is suspended until FIFO has some space, if FIFO was full.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Usually, the size of message is unknown beforehand. So set “1” as the byte to be transferred when the
command is issued first, and then decide the number of bytes to be received after the second byte by checking
the message code received.
Message_Out(19H)
Executes the message-out phase..
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
CPU sets the byte size of message to be received in NON-DMA data-size register before issuing this command.
After setting the message-out phase, the IC enters the byte size of message set into FIFO.
If FIFO becomes full, REQ-ACK hand-shake is suspended until CPU read out message from FIFO to make
some space in it.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Usually, the size of message is unknown beforehand. So set “1” as the byte to be transferred when the
command is issued first, and then decide the number of bytes to be received after the second byte by checking
the message code received.
In Initiator mode
CPU sets the byte size of message to be sent in NON-DMA data-size register before issuing this command.
CPU writes the message to be transferred in FIFO.
The IC acts as follows:
Asserts XSATN.
Negates XSACK if it is asserted at the start of execution.
Sends data in FIFO after checking the message phase at the timing when XSREQ is asserted.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
Negates XSATN after sending the bytes to be transferred.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
