S1R72803F00A
EPSON
53
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x1C
RetryLimit_H
7: SecLimit[2]
Dual Phase Retry Limit
6: SecLimit[1]
R/W
Second Limit
5: SecLimit[0]
4: CycLimt[12]
0x00
0x00
–
3: CycLimt[11]
2: CycLimt[10]
1: CycLimt[9]
0: CycLimt[8]
0x1D
RetryLimit_L
7: CycLimt[7]
R/W
Cycle Limit
6: CycLimt[6]
5: CycLimt[5]
If (SecLimit == 0 and CycLimit==0)
4: CycLimt[4]
Dual Phase is ignore
0x00
0x00
–
3: CycLimt[3]
2: CycLimt[2]
1: CycLimt[1]
0: CycLimt[0]
Dual Retry Time Set Register (Higher Rank, Lower Rank)
This register is used for the Dual Phase Retry protocol to set a retransmit retry time limit when an Async Transmit
packet is transmitted and a Busy is returned. When this register is “0”, the Dual Phase retry is ignored.
0x1C
Bit7..5 Second_Limit[2:0]
Set a Dual Phase Retry Time (Unit: second).
0x1C, 0x1D
Cycle Limit[12:0]
Sets a retry time at Cycle Limit [12:0] (Unit: 125
µ
s).
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x1B
PriReqCnt
7:
0:
1:
6:
0:
1:
5: PriReq[5]
4: PriReq[4]
0x00
0x00
0x00
3: PriReq[3]
R/W
Maximum Number of certain Priority Arb Request
2: PriReq[2]
1: PriReq[1]
0: PriReq[0]
Priority Request Count Register
This register shows registers in the pri-req field shown in the PRIORITY_BUDGET(CSR) register. This
register can precede the Priority Request as often as it is set to PriReq in a uniform section. But this register
can only be set by the node suitable for the bus manager.
Bit7..6 Reserved
Bit5..0 pri_req[9:0]
This bit is for setting the value of pri_req designated by the bus manager. Any value exceeding the value of
pri_max to be packaged with the firmware cannot be set. The value is cleared to zero when a uniform section
ends.
