S1R72803F00A
EPSON
81
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x63
IDE_PioDmaCyc 7: Assert Pulse[3]
6: Assert Pulse[2] R/W
IDE Transfer Mode Strobe Signal Assert Pulse
5: Assert Pulse[1]
Width Minimum Value
4: Assert Pulse[0]
0x00
0x00
–
3: Negate Pulse[3]
2: Negate Pulse[2] R/W
IDE Transfer Mode Strobe Signal Negate Pulse
1: Negate Pulse[1]
Width Minimum Value
0: Negate Pulse[0]
IDE PIO/DMA Cycle Register
This register sets a transfer mode when transferring data through the IDE interface. It is enabled for an access to 0x70
of the IDE-CSO Register.
It is common to both PIO/DMA modes.
Bit7::4 Asset Pulse
Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Bit3::0 Negate Pulse
Decides the minimum value of the negate period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Example: 0000: 2 x 20ns = 40ns
0001: 3 x 20s = 60ns
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x64
IDE_UltraDmaCyc 7:
0:
1:
6:
0:
1:
5:
0:
1:
4:
0:
1:
0x00
0x00
–
3: Cycle Time[3]
2: Cycle Time[2]
R/W IDE Ultra DMA Transfer Mode Strobe Signal
1: Cycle Time[1]
Minimum Cycle Time
0: Cycle Time[0]
IDE UltraDMA Cycle Register
This register sets a transfer mode when transferring data by the Ultra-DMA through the IDE interface.
Bit7::4 Assert Pulse
Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Bit3::0 Cycle Pulse
Decides the minimum cycle time of the strobe signal when transferring Ultra-DMA data through the IDE
interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle.
Example: 0000: 2 x 20ns = 40ns
0001: 3 x 20s = 60ns
