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Epson Research and Development
Vancouver Design Center
S1D13506
S5U13506P00C100 PCI Evaluation Board User Manual
X25B-G-014-02
Issue Date: 2009/03/02
4 Technical Description
The S5U13506P00C100 operates with both PCI and non-PCI evaluation platforms. It
supports passive LCD panels (4/6/16-bit), TFT/D-TFD panels (9/12/18-bit), CRT displays
(analog RGB output) and TV (NTSC and PAL).
4.1 PCI Bus Support
The S5U13506P00C100 does not have on-chip PCI bus interface support. The
S5U13506P00C100 uses the PCI FPGA to support the PCI bus.
4.2 Non-PCI Host Interface Support
The S5U13506P00C100 is specifically designed to support a standard PCI bus
environment (using the PCI Bridge Adapter FPGA). However, the S5U13506P00C100 can
directly support many other Host Bus Interfaces. When the FPGA is disabled (using jumper
JP7), headers H1 and H2 provide the necessary IO pins to interface to the Host Bus Inter-
faces listed in Table 4-4:, “CPU Interface Pin Mapping”.
Note
The S5U13506P00C100 is designed to work only with 3.3V systems. To use it with a
5V system, some modifications must be done to the board as follows:
1. Replace the 3.3V DRAM (U6) on the board with a 5V DRAM.
2. Cut the trace between JP9-2 and JP9-3 on the solder side of the board.
3. Connect JP9-1 and JP9-2. This will set IOVDD to 5V.
