Epson Research and Development
Page 19
Vancouver Design Center
S5U13506P00C100 PCI Evaluation Board User Manual
S1D13506
Issue Date: 2009/03/02
X25B-G-014-02
4.3.1 LCD Interface Pin Mapping
Note
1
For FPDATxx to LCD interface hardware connections refer to the Display Interface
AC Timing section of the
S1D13506 Hardware Functional Specification
, document
number X25B-A-001-xx.
2
The S5U13506B00C was designed using S1D13506 pin 75 (LCDPWR) to
control the
LCD bias power. This design is
no longer supported
. Applications should use one of
the available GPIO pins to control the LCD bias power allowing for software control
of power sequencing delays. For further information on LCD power sequencing, see
the
S1D13506 Programming Notes and Examples
, document number X25B-G-003-
xx.
Table 4-7: LCD Signal Connector (J4)
S1D13505
Pin Names
Connector
Pin No.
Monochrome Passive
Panels
Color Passive Panels
Color TFT/D-TFD
Panels
Single
Dual
Single
Single
Format 1
Single
Format 2
Single
Dual
4-bit
8-bit
8-bit
4-bit
8-bit
8-bit
16-Bit
8-bit
16-bit
9-bit
12-bit
18-bit
FPDAT0
1 and 6
D0
LD0
D0
D0
D0
LD0
LD0
R2
R3
R5
FPDAT1
3
D1
LD1
D1
D1
D1
LD1
LD1
R1
R2
R4
FPDAT2
5
D2
LD2
D2
D2
D2
LD2
LD2
R0
R1
R3
FPDAT3
7
D3
LD3
D3
D3
D3
LD3
LD3
G2
G3
G5
FPDAT4
9
D0
D4
UD0
D0
D4
D4
D8
UD0
UD0
G1
G2
G4
FPDAT5
11
D1
D5
UD1
D1
D5
D5
D9
UD1
UD1
G0
G1
G3
FPDAT6
13 and 4
D2
D6
UD2
D2
D6
D6
D10
UD2
UD2
B2
B3
B5
FPDAT7
15
D3
D7
UD3
D3
D7
D7
D11
UD3
UD3
B1
B2
B4
FPDAT8
17
D4
LD4
B0
B1
B3
FPDAT9
19
D5
LD5
R0
R2
FPDAT10
21
D6
LD6
R1
FPDAT11
23
D7
LD7
G0
G2
FPDAT12
25
D12
UD4
G1
FPDAT13
27
D13
UD5
G0
FPDAT14
29
D14
UD6
B0
B2
FPDAT15
31
D15
UD7
B1
FPSHIFT
33
FPSHIFT
DRDY
35 and 38
MOD
FPSHIFT2
MOD
DRDY
FPLINE
37
FPLINE
FPFRAME
39
FPFRAME
GND
2 and 8-26
(Even Pins)
GND
N/C
28
N/C
N/C
30
N/C
LCDVCC
32
+5V or +3.3V according to JP5
+12V
34
+12V
N/C
36
N/C
NC (pin 75)
2
40
Panel Enable, active low (LCDPWR)
2
= Driven low
