Epson S5U13506P00C100, User Manual

Page 1: ...d use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark...

Page 2: ...Page 2 Epson Research and Development Vancouver Design Center S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B G 014 02 Issue Date 2009 03 02 THIS PAGE LEFT BLANK ...

Page 3: ...I Bus Support 14 4 2 Non PCI Host Interface Support 14 4 2 1 CPU Interface Pin Mapping 15 4 2 2 CPU Bus Connector Pin Mapping 16 4 3 LCD Support 18 4 3 1 LCD Interface Pin Mapping 19 4 3 2 Buffered LCD Connector 20 4 4 CRT TV Support 21 4 4 1 CRT TV Interface Pin Mapping 21 4 4 2 CRT Support 21 4 4 3 TV Support 21 4 5 Current consumption measurement 21 5 References 22 5 1 Documents 22 5 2 Document...

Page 4: ...Page 4 Epson Research and Development Vancouver Design Center S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B G 014 02 Issue Date 2009 03 02 THIS PAGE LEFT BLANK ...

Page 5: ...100 PCI Evaluation Board The S5U13506P00C100 is designed as an evaluation platform for the S1D13506 Color LCD CRT TV Controller chip This document is updated as appropriate Please check the Epson Research and Devel opment website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via...

Page 6: ...using on board PCI bridge Headers for connecting to a 3 3V host bus interface 5V host bus interface also possible with modifications to the board 1Mx16 EDO DRAM Configuration options Headers for S1D13506 current consumption measurements 4 8 bit 3 3V or 5V monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V color passive LCD panel support 9 12 18 bit 3 3V or 5V TFT D TFD LCD panel support Em...

Page 7: ...506 LCD controller settings to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The S1D13506 LCD controller has 16 configuration inputs MD 15 0 which are read on the rising edge of RESET Where appropriate the S5U13506P00C100 hard wires some of these configuration inputs but in order to configure the S1D13505 for multiple host bus interfaces an eight position DIP swi...

Page 8: ...T is always driven WAIT is tristated when S1D13506 is not selected S1 2 MD1 See Table 3 2 Host Bus Interface Selection on page 8 S1 3 MD2 S1 4 MD3 S1 5 MD4 Little Endian Big Endian S1 6 MD5 WAIT is active high WAIT is active low S1 7 MD11 See Table 3 2 Host Bus Interface Selection on page 8 S1 8 MD12 BUSCLK input divided by 2 BUSCLK input not divided Required configuration when used in a PCI envir...

Page 9: ...ed in a PCI environment JP1 must be set to the 1 2 position Figure 3 2 Configuration Jumper JP1 Location Table 3 3 Jumper Settings Jumper Function Position 1 2 Position 2 3 Jumper Off JP1 BUSCLK Selection BUSCLK from U2 oscillator BUSCLK from H2 header n a JP2 CLKI Selection CLKI from U3 oscillator CLKI is the same as BUSCLK n a JP3 VDD current Normal operation n a Current measurement for VDD JP4 ...

Page 10: ...sition 2 3 the CLKI source is the same as BUSCLK provided by the non PCI host system Figure 3 3 Configuration Jumper JP2 Location JP3 VDD current JP3 allows the measurement of S1D13505 VDD current consumption When the jumper is at position 1 2 the evaluation board is operating normally default setting When no jumper is installed VDD current consumption can be measured by connecting an ammeter to J...

Page 11: ...lt setting When no jumper is installed DACVDD current consumption can be measured by connecting an ammeter to JP4 Figure 3 5 Configuration Jumper JP4 Location JP5 LCD panel voltage JP5 selects the voltage level to the LCD panel When the jumper is at position 1 2 the LCD panel voltage level is configured for 5 0V When the jumper is at position 2 3 the LCD panel voltage level is configured for 3 3V ...

Page 12: ...he LCDPWR signal is active low Figure 3 7 Configuration Jumper JP6 Location JP7 PCI FPGA Enable JP7 controls the PCI FPGA When no jumper is installed the PCI FPGA is enabled and the evaluation board may be used in a PCI environment default setting When the jumper is in position 1 2 the PCI FPGA is disabled and the evaluation board may be used with a non PCI host system Note Non PCI host system mus...

Page 13: ... JP8 selects the magnitude of the IREF current used by the embedded RAMDAC When the jumper is at position 1 2 the IREF current is 4 6mA This setting is used for CRT display When the jumper is at position 2 3 the IREF current is 9 2mA This setting is used for TV display but it may be used by CRT display as well Figure 3 9 Configuration Jumper JP8 Location JP8 IREF 9 2mA IREF 4 6mA ...

Page 14: ... PCI Host Interface Support The S5U13506P00C100 is specifically designed to support a standard PCI bus environment using the PCI Bridge Adapter FPGA However the S5U13506P00C100 can directly support many other Host Bus Interfaces When the FPGA is disabled using jumper JP7 headers H1 and H2 provide the necessary IO pins to interface to the Host Bus Inter faces listed in Table 4 4 CPU Interface Pin M...

Page 15: ...17 A14 A17 CARDIOWR CARDIOWR AB 16 13 A 16 13 A 16 13 SA 16 13 A 16 13 A 16 13 A 15 18 A 16 13 Connected to VDD AB 12 1 A 12 1 A 12 1 SA 12 1 A 12 1 A 12 1 A 19 30 A 12 1 A 12 1 A 12 1 AB0 A01 A01 SA0 LDS A0 A31 A01 A0 A0 DB 15 8 D 15 0 D 15 8 SD 15 0 D 15 8 D 31 24 D 0 7 D 15 0 D 23 16 D 23 16 DB 7 0 D 7 0 D 7 0 SD 7 0 D 7 0 D 23 16 D 8 15 D 7 0 D 31 24 D 31 24 WE1 WE1 WE1 SBHE UDS DS BI CE2 CARD...

Page 16: ...6 10 Connected to DB7 of the S1D13506 11 Ground 12 Ground 13 Connected to DB8 of the S1D13506 14 Connected to DB9 of the S1D13506 15 Connected to DB10 of the S1D13506 16 Connected to DB11 of the S1D13506 17 Ground 18 Ground 19 Connected to DB12 of the S1D13506 20 Connected to DB13 of the S1D13506 21 Connected to DB14 of the S1D13506 22 Connected to DB15 of the S1D13506 23 Connected to RESET of the...

Page 17: ...to AB8 of the S1D13506 12 Connected to AB9 of the S1D13506 13 Connected to AB10 of the S1D13506 14 Connected to AB11 of the S1D13506 15 Connected to AB12 of the S1D13506 16 Connected to AB13 of the S1D13506 17 Ground 18 Ground 19 Connected to AB14 of the S1D13506 20 Connected to AB15 of the S1D13506 21 Connected to AB16 of the S1D13506 22 Connected to AB17 of the S1D13506 23 Connected to AB18 of t...

Page 18: ...els All necessary signals are provided on the 40 pin LCD connector J1 The interface signals are alternated with grounds on the cable to reduce cross talk and noise When supporting an 18 bit TFT D TFD panel the S1D13505 can display 64K of a possible 256K colors because only 16 of the18 bits of LCD data are available from the S1D13505 For details refer to the S1D13506 Hardware Functional Specificati...

Page 19: ... No Monochrome Passive Panels Color Passive Panels Color TFT D TFD Panels Single Dual Single Single Format 1 Single Format 2 Single Dual 4 bit 8 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 8 bit 16 bit 9 bit 12 bit 18 bit FPDAT0 1 and 6 D0 LD0 D0 D0 D0 LD0 LD0 R2 R3 R5 FPDAT1 3 D1 LD1 D1 D1 D1 LD1 LD1 R1 R2 R4 FPDAT2 5 D2 LD2 D2 D2 D2 LD2 LD2 R0 R1 R3 FPDAT3 7 D3 LD3 D3 D3 D3 LD3 LD3 G2 G3 G5 FPDAT4 9 D0 D...

Page 20: ...anual X25B G 014 02 Issue Date 2009 03 02 4 3 2 Buffered LCD Connector J4 provides the same LCD panel signals as those directly from S1D13505 but with voltage adapting buffers which can be set to 3 3V or 5V Pin 32 on this connector provides power for the LCD panel logic at the same voltage as the buffer power supply ...

Page 21: ...bled 4 4 3 TV Support The S1D13506 supports PAL or NTSC TV output Composite Video is available on connector J1 and S Video is available on connector J3 An external current reference is implemented to provide the necessary RAMDAC output gain The reference current should be set to 9 2mA using jumper JP8 TV output is not available when CRT output is enabled PAL and NTSC modes cannot be enabled at the...

Page 22: ...e Date 2009 03 02 5 References 5 1 Documents Epson Research and Development Inc S1D13506 Hardware Functional Specification Document Number X25B A 001 xx Epson Research and Development Inc S1D13506 Programming Notes and Examples Document Number X25B G 003 xx 5 2 Document Sources Epson Research and Development Website http www erd epson com ...

Page 23: ...er 3x1 0 1 pitch unshrouded SIP3 7 3 JP3 JP4 JP7 Header 2x1 0 1 pitch unshrouded SIP2 8 1 J1 C VIDEO CUI RCJ 014 9 1 J2 VGA CONNECTOR DB15 PS2CO N NorComp 181 015 213R561 or equivalent 105 1 J3 S VIDEO Kycon KMDGX 4S BS 99 or equivalent Mini DIN 4 pin 11 1 J4 CON40A HDR2X20A Samtec TST 120 01 G D or equivalent 12 5 L1 L2 L3 L4 L5 Ferrite Bead INDUCTOR1 Steward 28F0181 ISR 10 13 1 Q1 MMBT2222A SOT2...

Page 24: ...3 3 DDPAK 2 Linear Technologies LT1117CM 3 3 28 1 U6 DRAM 1Mx16 SOJ Lead free SOJ42 ISSI IS41LV16100B 50KL 29 1 U7 LT1117CST 3 3 Linear Technologies LT1117CST 3 3 30 1 U8 INVERTER SINGLE NC7S04 SC70 5 Fairchild Semiconductor NC7S04P5 31 3 U9 U10 U11 74AHC244 SO20W TI 74AHC244 32 1 U14 EPF6016TC14 4 2 TQFP144 Altera EPF6016TC144 2 33 1 U15 EPC1PI8N DIP8 Altera EPC1PI8N programmed socketed Item Quan...

Page 25: ...8 0 1uF C8 0 1uF AB0 3 AB1 2 AB2 1 AB3 128 AB4 127 AB5 126 AB6 125 AB7 124 AB8 123 AB9 122 AB10 121 AB11 120 AB12 119 AB13 118 AB14 117 AB15 116 AB16 115 MA0 61 MA1 63 MA2 65 MA3 67 MA4 66 MA5 64 MA6 62 MA7 60 MD0 35 MD1 37 MD2 39 MD3 41 MD4 43 MD5 45 MD6 47 MD7 49 MD8 48 MD9 46 MD10 44 MD12 40 MD13 38 FPFRAME 73 FPLINE 74 FPSHIFT 77 FPDAT0 79 FPDAT1 80 FPDAT2 81 FPDAT3 82 FPDAT5 84 FPDAT6 85 FPDA...

Page 26: ...5 1 WAIT always driven 0 WAIT is tristated Note Chip has internal tie low resistors 2 0 S5U13505 6B00C PCI Bus DRAM Configuration CRT Output 2 5 Thursday October 03 2002 B Epson Research Development Inc Title Size Document Number Rev Date Sheet of MA 9 0 MD 15 0 MA5 MA8 MA6 MA4 MA2 MA3 MA1 MA7 MA0 MA9 MD2 MD11 MD0 MD6 MD2 MD11 MD9 MD0 MD13 MD3 MD4 MD15 MD 15 0 MD1 MD7 MD6 MD4 MD10 MD10 MD3 MD9 MD1...

Page 27: ...of 2 0 Epson Research Development Inc S5U13505 6B00C PCI Bus LCD Headers B 3 5 Monday December 11 2006 COLOR MONO LCD CONNECTOR Note 244 input side violates the spec of chip At 5V 244 logic high needs to be greater than 3 7V Our chip if set for 3 3V will not meet this input requirement of the 244 Input on 244 can take upto 5 5V as input high 1 2 3 JP6 LCD PW R SELECT JP6 LCD PW R SELECT 1 3 5 7 9 ...

Page 28: ... 12V 5V 5V 5V 12V 5V 12V 5V C35 33uF 20V 10 PCIB1 PCI B 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 12V TCK GND TDO 5V 5V INTB INTD PRSNT 1 RESERVED PRSNT 2 RESERVED GND CLK GND REQ VI O AD31 AD29 GND AD27 AD25 3 3V C BE3 AD23 GND AD21 AD19 3 3V AD17 C BE2 GND IRDY 3 3V DEVSEL G...

Page 29: ...29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 IO1 IO2...

Page 30: ...son Research and Development Vancouver Design Center S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B G 014 02 Issue Date 2009 03 02 8 Board Layout Figure 8 1 S5U13506P00C100 Evaluation Board Layout ...

Page 31: ...5522 FAX 86 21 5423 5512 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 FAX 852 2827 4346 Telex 65542 EPSCO HX SHENZHEN BRANCH 12F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen 518057 CHINA Phone 86 755 2699 3828 FAX 86 755 2699 3838 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 FAX 886...

Page 32: ...elopment Vancouver Design Center S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B G 014 02 Issue Date 2009 03 02 Change Record X23A G 014 02 Revision 2 0 update sales offices X23A G 014 01 Revision 1 0 initial release ...