Connectors
14
Seiko Epson Corporation
S5U13L01P00C100 Evaluation Board
Rev. 1.3
Chapter 4 Connectors
4.1 CN1, CN2, CN5 Panel Interface Connector
The LCD interface uses the VS, HS, DE, PCLK and PDT[23:0] pins. All signals on these pins are available on
connectors CN1, CN2 and CN5.
Connectors CN1 and CN2 and CN5 are 0.1” x 0.1”, 40-pin headers (20 x 2) for CN1, 16-pin headers (8 x 2) for CN2,
0.5mm pitch, 40-pin FPC Connector for CN5. See Figure 4-1: “Host and Panel Bus Connector Location (CN1, CN2,
CN3, CN4, CN5)” on page 15 for the location of these connectors. For the pinout of connectors CN1, CN2 and
CN5, see Section Chapter 7, “Schematic Diagrams” on page 23.
Note
Connector CN1 and CN2 are only land.
4.2 CN3, CN4 Host Bus Interface Connector
All S1D13L01 host interface pins are available on connectors CN3 and CN4. This allows the S5U13L01P00C100
evaluation board to be connected to a variety of development platforms. For S1D13L01 host interface pin mapping,
see Table 3-1: “Host Interface Pin Mapping,” on page 7.
See Figure 4-1: “Host and Panel Bus Connector Location (CN1, CN2, CN3, CN4, CN5)” on page 15 for the location
of host bus connectors CN3 and CN4. CN3 and CN4 are 0.1” x 0.1” 26-pin header (13x2). For the pinout of
connectors CN3 and CN4, see Section Chapter 7, “Schematic Diagrams” on page 23.
Note
Connector CN3 and CN4 are only land.
