ETK-S6.0 - User’s Guide
41
ETAS
Technical Data
7.7
Testcharacteristics
Parameter
Symbol Condition
Min Typ
Max Unit
Reset delay 1
1)
t
Reset1
U
Batt
= 12 V
USG = 0 V
3.3 V
without transferring
FPGA
29
40
ms
Reset delay 2
2)
t
Reset2
U
Batt
= 0 V
12 V
transfer FPGA
100
240 ms
AUD-II interface
clock
3)
20/10
MHz
JTAG interface
clock
4)
20
MHz
JTAG interface
clock
5)
20
6)
MHz
1)
: Delay of ECU reset through ETK without transferring the FPGA (U
Batt
present, USG will be switched on)
2)
: max. delay of ECU reset through ETK (U
Batt
and USG will be switched on)
3)
: configurable
4)
: generated by ETK if ETK is operating in H-UDI mode (configuration B)
5)
: for attached debugger
6)
: must be less than periphal clock P
