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PI-P5BVLL User`s Manual
3.4 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset.
This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache.
It also coordinates communications between the conventional ISA
bus and the PCI bus.
It must be stated that these items should never need to be altered.
The default settings have been chosen because they provide the best
operating conditions for your system.
The only time you might consider making any changes would be if
you discovered that data was being lost while using your system.
Phoenix-Award BIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
[By SPD]
x CAS Latency Time
[Auto]
x Dram RAS# to CAS# Delay
[Auto]
x DRAM RAS# Precharge
[Auto]
x Precharge dealy (tRAS)
[Auto]
x System Memory Frequency
[By SPD]
System BIOS Cacheable
[Enabled]
Memory Hole At 15M-16M
[Disabled]
►
PCI Express Root Port Func
[Press Enter]
**VGA Setting**
On-Chip Frame Buffer Size
[ 8MB]
DVMT Mode
[DVMT]
DVMT / FIXED Memory Size
[128MB]
Boot Display
[3]
Lan1 Chip Control
Lan2 Chip Control
[Enabled]
[Enabled]
Item Help
Menu Level
►
↑↓←
→
：
Move Enter: Select +/-/PU/PD: Value F10:Save Esc: Exit F1:General
Help F5:Previous Value F6:Fail-Safe Defaults F7:Optimized Default
(Figure 8)
Summary of Contents for PI-P5BVLL
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Page 17: ...PI P5BVLL User s Manual 9 Jumper Locations on the PI P5BVLL...
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