SD20-G Series
233
2
b)
32-bit Division
Instruction format:[DIVD□□ X Y Z]
Instruction Description:
DIVD is division instruction, □□is instruction execution register area, X is
divisor, Y is dividend, Z is store result area; The result of instruction execution is Z=X/Y, which means
that the value of register address in X area divided by the value of register address in Y area, the result
sends to Z register address, of which integer of divisor stores to low-bit register address, remainder stores
to high-bit register address; User can operate for R area, P area and immediate operand; See details as
table 8.1.10.
Table 8.1.10 32-bit Division Instruction Syntax, Results and related Annotations
Syntax Expression
Running Results
Annotations
DIVDRR R1 R2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing the values of R area, the result stores to
no.3~no.6 registers, integer stores to no.3 and no.4
registers, remainder stores to no.6 and no.5 registers.
DIVDDR L1 R2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing immediate operand and the value of R
register, the result saves to no.3~no.6 registers, integer
stores to no.3 and no.4 registers, remainder stores to
no.6 and no.5 registers.
DIVDPR P1 R2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing the value of P register and R register, the
result saves to no.3~no.6 registers, integer stores to
no.3 and no.4 registers, remainder stores to no.6 and
no.5 registers.
DIVDDP L1 P2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing immediate operand and the value of P
register, the result saves to no.3~no.6 registers, integer
stores to no.3 and no.4 registers, remainder stores to
no.6 and no.5 registers.
DIVDRP R1 P2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing the value of R register and P register, the
result saves to no.3~no.6 registers, integer stores to
no.3 and no.4 registers, remainder stores to no.6 and
no.5 registers.
DIVDPP P1 P2 R3
R4 R3=R2 R1/R3 R2
R6 R5=R2 R1%R3 R2
Dividing the value of 2 registers in P area, the result
saves to no.3~no.6 registers, integer stores to no.3 and
no.4 registers, remainder store to no.6 and no.5
registers;
(5) Scaling Instruction
a) Scaling Division
Instruction Format: [QDIV□□ D X Y Z]
Instruction Description:
QDIV is instruction code, □□ is instruction execution register area, D is result scaling value, X is divisor,
Y is dividend, Z is result storing address;User can operate for R area, P area and immediate operand;
Summary of Contents for SD20-G Series
Page 35: ...SD20 G Series 35 M3 structure Fig 3 1 5 Servo drive structure 3...
Page 36: ...SD20 G Series 36 ML3 structure 118 5 5 7 5 93 297 8 223 118 93 0 5 12 5 7 5 4 M4...
Page 38: ...SD20 G Series 38 M4 structure Approx mass 10 365 kg Fig 3 1 7 Servo drive structure 5...
Page 39: ...SD20 G Series 39 M5 structure Approx msaa 11 1Kg Fig 3 1 8 Servo drive structure 6...
Page 40: ...SD20 G Series 40 M6 structure Approx mass 17 4Kg Fig 3 1 9 Servo drive structure 7...
Page 182: ...SD20 G Series 182 Fig 6 4 44SD20E Cam internal frameworkdiagram...
