M
ODEL
SL900A V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2006.06.30
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
37/51
SL900A
T
ECHNICAL
M
ANUAL
DPLL : Provides the DSP System Clock. DPLL can be programmed to provide 1x to 6x
output of the 13Mhz reference.
UPLL : Provides the USB System Clock.
11.2
Reset Generation Unit
Figure 38 shows reset scheme used in MT6226M. There are three kinds of resets in the MT6226M, i.e.,
hardware reset, watchdog reset, and software resets.
Figure 38. Reset Scheme used in MT6226M
- Hardware Reset
This Reset is inputted through the SYSRST# pin from PMIC(MT6305 Pin 24). The SYSRST# shall be
driven to low during power-on. The Hardware reset has a global effect on the chip. It initializes all
digital and analog circuits except the RTC. Refer to the listed below.
-
All Analog Circuits are turned off
-
All PLLs are turned off and bypassed. The 13Mhz system clock is the default time base.
-
Special Trap statue in GPIO.
- Watchdog Reset
A Watchdog reset is generated when the Watchdog timer expires as the MCU software failed to re-
program the timer counter in time. Hardware blocks that are affected by the watchdog reset are :
- MCU Subsystem
- DSP Subsystem
- External Component (By software program)
- Software Reset
These are local reset signals that initialize specific hardware. For example, The MCU or DSP software
may write to software reset trigger registers to reset hardware modules to their initial states, when
hardware failures are detected. The following Modules has software resets
-
DSP Core
-
DSP Coprocessors.
-
12.
Analog Front-End & Analog Blocks
Summary of Contents for SL900A
Page 1: ...SL900A SL900A ...
