Appendix - Power Requirements
ComTec GmbH
Appendix 8-8
For the above setup the GATE signal was delayed (i.e. shifted right) as long as no losses of
events occurred (observed in the MPANT software).
Fig. 8.8: ADC GATE hold time
The ADC GATE signal must be held valid until DRDY is removed.
Here the GATE delay was reduced (i.e. shifted left) as long as no event losses occurred.
NOTE:
DRDY is only removed after DACC was set and this may vary largely (see Fig. 8.5).