2007-11-19
Page 18 of 35
IT321_Tech_doc_12
4.2 Power supply
The IT321 module requires only one power supply VDD, which can be
supplied directly from a battery since the module has internal regula-
tors. Keep the supply active all the time in order to keep the non-
volatile RTC & RAM active for fastest possible TTFF.
Main power supply VDD current varies according to the processor
load and satellite acquisition. Typical VDD peak current is 45mA dur-
ing acquisition. Typical VDD current in low power Hibernate mode is
20uA.
The IT321 allows about 300mVpp ripple voltage at the supply VDD
below 10kHz frequency. The ripple voltage should be reduced further
at VDD supply below 3mVpp at 100kHz frequency or higher. E.g. if
the battery that provides the supply for VDD is connected to a
switched mode regulator operating at 100kHz, the resulting voltage
ripple shall be reduced below 3mVpp by a suitable by-pass capacitor
or by external low pass filter prior VDD supply input.
4.3 Configuration select: GPIO 6 & 2
The data output protocol configuration is defined using the GPIO 6
and 13 control inputs. After power up the value is read and the con-
figuration is processed according the Table 3 (in previous chapter).
The GPIO 6&2 inputs should be kept valid after power up for at least
500 ms to allow the internal power-on-reset delay to settle. I/O levels
are CMOS 1.8V compatible.
4.4 Boot Control inputs
The boot source is defined in the internal boot ROM sector by using
the BOOT1 and BOOT2 control inputs. After power up the value is
read and the boot is processed according the Table 4 (in previous
chapter).
The BOOT inputs should be kept valid after power up for at least 500
ms to allow the internal power-on-reset delay to settle. I/O levels are
CMOS 1.8V compatible.
Summary of Contents for IT321
Page 15: ...2007 11 19 Page 15 of 35 IT321_Tech_doc_12 Figure 2 SiRFFlash utility settings...
Page 25: ...2007 11 19 Page 25 of 35 IT321_Tech_doc_12 Figure 7 Tape and reel specification...
Page 32: ...2007 11 19 Page 32 of 35 IT321_Tech_doc_12 7 3 Circuit drawing rev C...
Page 34: ...2007 11 19 Page 34 of 35 IT321_Tech_doc_12 7 6 Artwork layer 2 rev C 7 7 Artwork layer 3 rev C...
Page 35: ...2007 11 19 Page 35 of 35 IT321_Tech_doc_12 7 8 Artwork layer 4 Bottom rev C...
