3 Application Interface
Copyright © Fibocom Wireless Inc.
33
+3.3V
RESET#
Module State
Initialization
Activation
FCPO#
typical TBD
Activation
t
off
Finalization
OFF
AT+CPWROFF
t
off1
t
on1
t
sd
Figure 11. Reset timing 2
nd
Index Min.
Recommended Max. Comment
t
off1
270ms 300ms
-
FCPO# should be asserted after RESET#,
refer section 3.3.2
t
off
500ms 500ms
-
Time to allow the WWAN module to fully
discharge any residual voltages before the pin
could be de-asserted again. This is required for
both Pre-OS as well as Runtime flow
t
on1
8ms
20ms
-
RESET# should be de-asserted after FCPO# assert
to high,
refer section 3.3.1.2
RESET# is a sensitive signal, it’s recommended to add a filter capacitor close
to the module. In case of PCB layout, the RESET# signal lines should keep
away from the RF interference and protected by GND. Also, the RESET# signal
lines shall neither near the PCB edge nor route on the surface planes to avoid
module from reset caused by ESD problems.
