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FIBOCOM_NL952-NA_Hardware_User_Manual
Page 26 of 57
Index Min.
Recommended Max.
Comments
t
off1
TBD
TBD
-
RESET# should be asserted after PERST#,
refer
t
off2
TBD
TBD
-
FCPO# should be asserted after RESET#,
refer
t
off
TBD
TBD
-
Time to allow the WWAN module to fully discharge any
residual voltages before the pin could be de-asserted
again. This is required for both Pre-OS as well as Runtime
flow
t
on1
TBD
TBD
-
RESET# should be de-asserted after FCPO#,
refer
t
on2
TBD
TBD
-
The time delay of PERST# de-asserted after FCPO#,
PERST# must always be the last to get de-asserted.
refer
Note
:
When USB is used as data transfer interface, follow timing above in PERST# connecting with
host, otherwise don’t control PERST# in PERST# floating condition.
PCIe Link State
3.3.4.1 D0 L1.2
Module supports PCIe goes into D0 L1.2 state in Win10 system. The D0->D0 L1.2@S0/S0ix->D0 timing
is shown in figure 3-10:
Figure 3-10 D0 L1.2 timing
Note
:
When USB is used as data transfer interface in Chrome/Android/Linux OS, there is no PCIe link
state. But when USB goes into suspend it also needs to follow the timing above (If PERST# is
floating, don’t control PERST#).
+3.3V
PERST#
RESET#
Module State
D0 L1.2@S0/S0ix
D0
FCPO#
D0