Theory of Operation
Waveform Processing
2
2-19
Waveform Processing
2-34.
Overview
2-35.
An input signal takes AC and DC paths. With AC voltage or AC current functions, the
signal is sent directly to the Fast A/D Converter for digitizing. With DC voltage or DC
current functions, signals from the AC path and the DC path are recombined to form an
AC + DC signal. This combined signal is then applied to the Fast A/D Converter for
digitizing. Data from the Fast A/D Converter is then written into the digital ASIC. The
microprocessor controls the movement of this data to the display controller and the LCD
display.
Detailed Description
2-36.
The AC and DC components of the input signal are recombined at U9-3. U9 is
configured as a bandpass filter with a center frequency of 2 Hz (the crossover frequency
for the AC and DC signals.) Since the bandpass filter adds gain to the path at this
frequency, the frequency response of the overall circuit is improved. An inductor
(formed by C27, C95, C51, R76, R85, and the gyrator op-amp located in U30), R86, and
C67 make up the feedback network for the bandpass filter.
The following two analog switches allow for control of the signal flow:
•
The first switch (U14-1, U14-2, U14-10, and U14-15) interrupts the AC signal.
•
The second switch (U14-6, U14-11, U14-12, and U14-13) removes the inductor (the
gyrator circuit) from the feedback of U9.
For the DC path, the input signal conditioning circuitry scales the DC input to match the
gain factor used by the Slow A/D Converter. (The Slow A/D Converter uses one of three
gain factors, as required by the selected function and range.) As a result, a 30-mV, 300-
mV, or 3V full scale signal is provided to the Slow A/D Converter.
The AC path is scaled to output 300-mV full scale for all inputs.
For proper recombination with the AC signal, the DC signal provided to the Slow A/D
Converter must
be scaled to provide 300 mV
for all inputs. The necessary DC restoration
path is provided by U30, which contains the active circuitry necessary to scale the Slow
A/D Converter input by 0.1, 1, or 10. The DC signal to be scaled appears at the input to
the guard amplifier. The guard amplifier drives the compensation amplifier, which can be
configured for gain by selecting appropriate resistor pairs in Z6. For a gain of 0.1, 200-
k
Ω
and 20-k
Ω
resistors are selected. For a gain of 1, two 200-k
Ω
resistors are selected.
For a gain of 10, 200-k
Ω
and 2-M
Ω
resistors are selected. For a given function and
range, the proper gain is thereby selected to provide identical scaling for the AC and DC
paths.
The reconstructed (AC + DC) input signal must be given an additional DC bias to center
it in the unipolar input range of the Fast A/D Converter (approximately 0.4V to 1.6V dc).
R32 and R24 form a divider across the Fast A/D Converter reference circuitry that
establishes the midpoint of the Fast A/D Converter input range. A second divider (R78
and R63) then divides the midpoint divider output by 2 to compensate for a gain of 2 in
the next part of the circuit (the sum amplifier.) C89 and circuit resistance provide
filtering for the output of the second divider.
Summary of Contents for 863
Page 49: ...Maintenance Disassembly 3 3 5 OFF 1 6 Places 4 5 5 3 3 2 os5f eps Figure 3 1 Disassembly ...
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Page 96: ...6 1 Chapter 6 Schematic Diagrams Title Page 6 1 A1 Main PCA Assembly 6 3 ...
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