4. REMOTE OPERATION
Page 139
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Status Byte Register
(“
∗
STB?” or ”
∗
SRE
n”)
OPER
Bit7 (128)
←←←
OPERation summary bit
RQS/MSS
Bit6 (64)
Standard Event Status Register
(“
∗
ESR?” or “
∗
ESE
n”)
ESB
Bit5 (32)
←←←
PON
Bit7
URQ
Bit6
CMD
Bit5
EXE
Bit4
DDE
Bit3
QYE
Bit2
RQC
Bit1
OPC
Bit0
MAV
Bit4 (16)
←←←
OUTPUT
QUEUE
N/A
Bit3 (8)
ERROR
Bit2 (4)
←←←
ERROR
QUEUE
N/A
Bit1 (2)
N/A
Bit0 (1)
Figure 13.
Status Byte Register
The status byte register can be read using the “*STB?” query, or by performing a
serial poll on the IEEE-488 bus. If you read this using a serial poll then bit 6 is
the RQS. If the “
∗
STB?” query is used, then bit 6 is the MSS bit. All of the other
bits are common to both types of query.
Each of these status bits can cause a SRQ to occur. The Service Request
Enable Register (“
∗
SRE” program message ) determines which of these flags are
able to assert the SRQ line. This enable register has a matching set of bits that each
will enable the designated bit to cause a SRQ, except for the RQS/MSS bit(s)
which cannot cause a SRQ. If you set this register to 20 ($14 hex), an SRQ will occur
if the MAV or the ERROR bit are set. The description of these bits are given as:
•
OPER:
OPERational event register summary bit (Bit 7)
This bit is not supported by the .
•
RQS:
Requested Service (Bit 6)
Indicates that the SRQ line of the IEEE-488 interface has been asserted by
the . This bit is cleared when a serial poll is performed on the
, and is a part of the status byte register when read using a serial
poll. This bit does not apply if the COM1 port is being used.
•
MSS:
Master Summary Status (Bit 6)
Indicates that an event or events occurred that caused the to
request service from the Host, much like the RQS bit. Unlike the RQS bit, it
is READ ONLY and can be only cleared when the event(s) that caused the
service request are cleared.
•
ESB:
Event Summary Bit (Bit 5)
Indicates if an enabled bit in the Standard Event Status Register became set.
(See Section 4.4.1.2.)
•
MAV:
Message Available Bit (Bit 4)
Indicates that at least one reply message is waiting in the IEEE-
488 output queue.
•
ERR:
Error Queue not empty (Bit 2)
Indicates that at least one command error message is waiting in the
IEEE-488 error message queue. Use the “SYSTem:ERRor?”
query to get this message.
