Force SPARC/CPCI-520G, Technical Reference Manual

Page 1: ...erved This document shall not be duplicated nor its contents used for any purpose unless written permission has been granted Copyright by Force Computers SPARC CPCI 52x G Technical Reference Manual P...

Page 2: ...ghts of Force Computers GmbH nor the rights of others All product names as mentioned herein are the trademarks or registered trademarks of their respective companies World Wide Web www forcecomputers...

Page 3: ...3 Solaris Installation 18 3 1 4 Terminal connection 20 4 Base 520 G Installation 21 4 1 Location Overview 21 4 2 Mechanical Construction 23 4 2 1 FORCE COMPUTERS UPA64S Card Installation 25 4 3 Poweri...

Page 4: ...3 Powering Up 57 5 4 Front Panel and Connectors 57 5 4 1 Ethernet 2 Interfaces 58 5 4 2 PMC Slots 59 5 4 3 CompactPCI Backplane Connector Pinout 59 5 5 SCSI 2 Configuration 62 5 6 Ethernet 2 Configura...

Page 5: ...6 4 SCSI Interface SYM53C875 97 6 5 PMC Slots with Busmode Support 98 7 FORCE OpenBoot Enhancements 101 7 1 System Configuration 102 7 1 1 System Configuration Register Accesses 102 7 1 2 LEDs Seven S...

Page 6: ...Contents Page iv SPARC CPCI 52x G...

Page 7: ...y configurations all data in MByte 18 Tab 8 Required Solaris Packages 19 Tab 9 Customizing Solaris 19 Tab 10 Location diagram of the Base 520 G schematic 22 Fig 7 Mechanical construction of a Base 520...

Page 8: ...Interrupt sources from the I O 52x G 73 Tab 34 UltraSPARC IIi PCI address space 8 GByte 74 Tab 35 PCIO EBus2 base address registers 77 Tab 36 EBus2 memory map in the PCI bus 4 GByte address space 77 T...

Page 9: ...tion see section 2 Introduction on page 5 the installation instructions a mechanical overview of the product initialization prerequisites and requirements the default configura tion for example the de...

Page 10: ...Bridge Sun SME2411 http www sun com UltraSPARC IIi Sun SME1040 http www sun com PCI I O Controller Sun STP2003QFP http www sun com PHYceiver ICS ICS1890 http www icsinc com PCI Ultra SCSI Fast 20 I O...

Page 11: ...M Inter rupt Control Register extended temperature sensor description Added descriptions for installing Solaris added description for OpenBoot plcc2tsop command version 3 10 4 or greater Added note fo...

Page 12: ...y the same word Also used for on screen output Variable Typical character format for words that represent a part of a command a programming statement or the like and that will be replaced by an applic...

Page 13: ...d and follow the safety notes of a section first before acting as documented in the other parts of the section Danger Dangerous situation serious injuries to people or severe damage to objects Caution...

Page 14: ...Using This Manual Page xii SPARC CPCI 52x G...

Page 15: ...by Force Computers or qualified persons in electronics or electrical engineering are authorized to install unin stall or maintain the SPARC CPCI 52x G The information given in this manual is meant to...

Page 16: ...nical specification of the respective components For the total power consumption of the SPARC CPCI 52x G see table 4 Maximum power supply values without UPA64S card and PMC modules on page 15 Ensure t...

Page 17: ...these 2 connectors may destroy your telephone as well as your SPARC CPCI 52x G Therefore Make sure that TPE connectors near your working area are clearly marked as network connectors Make sure that TP...

Page 18: ...Page 4 SPARC CPCI 52x G...

Page 19: ...ary L2 cache 1 Mbyte PLCC boot PROM and 2 Mbyte TSOP boot flash EPROM Up to 4 Mbyte user flash EPROM Interfaces Interfaces of the Base 520 G PCI bridge for 7 CompactPCI slots 10BaseT 100BaseTx Etherne...

Page 20: ...Introduction Page 6 SPARC CPCI 52x G...

Page 21: ...I O 2 ports with RS 232 configuration as factory option RS 422 I O on front panel or backplane Audio Port I O on front panel microphone and headphone or backplane Keyboard Mouse Port I O on front pane...

Page 22: ...onfirm availability of specific combi nations The table below explains the general product nomenclature Table 2 Nomenclature of the SPARC CPCI 52x G SPARC CPCI 52xG mmm sss c uu ggg x 0 x 2 x 3 Base 5...

Page 23: ...1 MByte L2 cache 2 MByte user flash EPROM and UPA64S slot SPARC MEM 50M 128 user upgradable memory module for slot 2 and 3 128 Mbyte 50M 256 user upgradable memory module for slot 2 and 3 256 Mbyte 50...

Page 24: ...Ordering Information Introduction Page 10 SPARC CPCI 52x G...

Page 25: ...he variant you have purchased from FORCE COMPUTERS see section 4 Base 520 G Installation on page 21 and see section 5 I O 52x G Installation on page 53 SPARC CPCI 52x G variants There are 4 variants a...

Page 26: ...I O 523G The dual segment variant is designed for Com pactPCI systems with a backplane consisting of 2 CompactPCI bus segments Figure 4 SPARC CPCI 523G schematic view SCSI SERIAL A B SERIAL A B Ether...

Page 27: ...Therefore FORCE COMPUTERS assumes that there usually is no need to exchange the Lithium battery except for example in the case of long term spare part handling Please observe the following Exchange t...

Page 28: ...quirements and free CompactPCI backplane slots due to your SPARC CPCI 52x G variant a system CompactPCI bus slot for the Base 520 G an additional system CompactPCI bus slot for the IO 523G on the righ...

Page 29: ...jack Always use at most one of the interfaces if an audio interface is avail able on both the front panel and the backplane Table 4 Maximum power supply values without UPA64S card and PMC modules CPU...

Page 30: ...input impedance maximum full scale input of 2 VRM Availability on backplane Stereo Aux 1 In Signal level 10 k input impedance maximum full scale input of 2 VRMS Availability on backplane Stereo Aux 2...

Page 31: ...pes as SPARC MEM 50x The Base 520 G can hold 1 to 4 memory modules providing up to 1 GByte DRAM capacity 1 memory module can carry 2 memory banks Note At least 1 lower memory module MEM 50L is require...

Page 32: ...memory modules can be installed and memory module 2 must be a SPARC MEM 50U i e an upper memory module Note the limitations given by the SPARC CPCI 52x G configuration under consideration see section...

Page 33: ...interactively these packages can be installed by selecting the proper software group in the Software dialog Customize the software groups as follows Table 9 Required Solaris Packages Package Descript...

Page 34: ...er consideration In case of several Wide SCSI devices insert the respective line per device Terminate the file with a 3 1 4 Terminal connection The SPARC CPCI 52x G provides 2 serial interfaces A and...

Page 35: ...el cache L2 cache a CompactPCI interface a boot PROM PLCC a boot flash EPROM TSOP and an user flash EPROM TSOP 3 connectors for the memory modules a connector for interfacing to a UPA64S card a connec...

Page 36: ...I O MEM 50L connectors P8 P9 P10 Top Boot PROM PLCC APB D I A G S C S I ETHERNET M O D E Front panel S E R I A L A B K B D Audio Serial I O L2 cache MIC PHYceiver XCVR UPA64S slot SW4 Bottom SW5 SW6 R...

Page 37: ...s for up to 4 memory modules With an installed UPA64S card only 2 memory modules are possible The following figures show the Base 520 G in possible configurations Figure 8 Mechanical construction of a...

Page 38: ...2 slot configuration with UPA64S card schematic Base 520 in 1st slot F r o n t p a n e l B a c k p l a n e CPU and cache with heatsink MEM 50L MEM 50U 1st of 2 slots Base 520G with up to 2 memory modu...

Page 39: ...O 52xG without UPA64S card 2 If you do not install an I O 52xG afterwards Remove the 2 z stand offs fixed on the UPA64S card by loosing the respective 2 screws and fix the UPA64S card again with 2 of...

Page 40: ...for initial powering up Booting The SPARC CPCI 52x G boot PROM consists of a 1 MByte PROM OTP PLCC socket device not writeable Alternatively a 2 MByte TSOP boot flash EPROM device can be enabled by S...

Page 41: ...n diagram of the Base 520 G sche matic on page 22 Note Before powering up the board check the current switch settings for consistency Do not switch during operation Table 11 Default switch settings Na...

Page 42: ...front panel termination automatic ON front panel termination disabled SW5 2 OFF SCSI termination for SCSI 1 on backplane OFF backplane termination disabled ON backplane termination enabled SW5 3 OFF R...

Page 43: ...ggled it instantaneously affects the SPARC CPCI 52x G by generating a push but ton external initiated reset XIR Push button exter nal initiated reset allows a user reset abort of part of the processor...

Page 44: ...low or green all colors either permanent or with a blinking frequency of ap proximately 0 5 1 or 2 Hz MIC Standard 3 5 mm microphone jack HDPH Standard 3 5 mm headphone jack ETHERNET Standard Twisted...

Page 45: ...2 In or Microphone In as factory option Audio Out Stereo Line Out 4 5 1 Audio Interface The 2 front panel audio interfaces use standard 3 5 mm phono jacks sup porting 1 single ended condenser microph...

Page 46: ...the J5 back panel connector via an MII 1 interface If Ethernet 1 gets accessed via I O panel the front panel connector is normally disabled automatically for other con figurations see the respective...

Page 47: ...standard SCSI cable to the front panel connector Table 16 50 pin SCSI connector pinout Signal Pin Connector Pin Signal GND 1 26 D0 GND 2 27 D1 GND 3 28 D2 GND 4 29 D3 GND 5 30 D4 GND 6 31 D5 GND 7 32...

Page 48: ...s front panel holds the signals for the 2 serial interfaces A and B SERIAL A B on the Base 520 G s front panel holds the signals for the 2 serial interfaces A and B Table 17 26 pin serial A B connect...

Page 49: ...Signal n c 1 14 CTS _B Input CTS _A Input 2 15 nc RTS _A Output 3 16 RTS _B Output RTS _A Output 4 17 nc CTS _A Input 5 18 nc nc 6 19 RTS _B Output RxD _A Input 7 20 RxD _A Input TxD _A Output 8 21 nc...

Page 50: ...e connector pinout above Pin 21 row C AUD MIN Mono In Pin 21 row B AUD RMICIN Right Micro In Pin 22 row B AUD LMICIN Left Micro In SCSI 1 D10 SCSI 1 REQ SCSI 1 ACK SCSI 1 D6 SCSI 1 D2 SCSI 1 D14 MII 1...

Page 51: ...anel or I O panel The I O panel supports the following interfaces Fast Wide SCSI 1 MII 1 Ethernet Serial A B interface Audio interface Keyboard Mouse Parallel interface and Floppy interface Danger The...

Page 52: ...of a valid SCSI 1 bus configura tion There are 4 valid Base 520 G switch settings corresponding to valid SCSI 1 bus configurations The following factors differentiate the valid SCSI 1 bus configuratio...

Page 53: ...FF backplane termination disabled Default configuration 2 for 8 bit SCSI The default configuration 2 is also covered by the default switch set ting the Base 520 G is not located at an endpoint of the...

Page 54: ...n is covered by the default switch set ting The Base 520 G is located at an endpoint of the SCSI 1 bus the SCSI 1 bus is extended via the CompactPCI backplane but no SCSI cable is plugged into the fro...

Page 55: ...C CPCI 52x G Ethernet address and the host ID are determined Figure 14 The 48 bit 6 byte Ethernet address Figure 15 The 32 bit 4 byte host ID ok banner 47 40 39 32 31 24 23 16 15 8 7 0 0 0 8 0 4 2 Byt...

Page 56: ...World Wide Web site 4 8 1 Boot the System The most important function of OpenBoot firmware is the booting of the system Booting is the process of loading and executing a stand alone program such as th...

Page 57: ...lue of boot file NVRAM parameter The NVRAM parameters used for booting are described in the following section bootoption Boot option may be one of the following a a prompt interactively for the device...

Page 58: ...OpenBoot Firmware Base 520 G Installation Page 44 SPARC CPCI 52x G...

Page 59: ...disk2 disk SCSI target ID 2 disk1 disk SCSI target ID 1 disk0 disk SCSI target ID 0 tape or tape0 1st tape drive SCSI target ID 4 tape1 2nd tape drive SCSI target ID 5 cdrom CD ROM partition f SCSI t...

Page 60: ...NVRAM configura tion parameters If the parameter diag switch is false boot device and boot file are used Otherwise the OpenBoot firmware uses diag device and diag file for booting 4 8 3 Diagnostics A...

Page 61: ...these routines Examples SCSI bus To check the SCSI 1 for connected devices enter Table 22 Diagnostic routines Command Description probe scsi Identifies devices connected to the primary SCSI bus probe...

Page 62: ...ponse depends on the self test of the device node Group of devices To test a group of installed devices enter All devices below the root node of the device tree are tested The re sponse depends on the...

Page 63: ...he OpenBoot firmware The ID PROM contains specific information to the individual machine including the serial number date of manufacture and assigned Ethernet address The following table lists these c...

Page 64: ...e categories may also contain subcategories To get help for special Forth words or subcat egories just type help name The online help shows you the Forth word the parameter stack before and after exec...

Page 65: ...l address x addr display the 64 bit number from location addr l addr display the 32 bit number from location addr w addr display the 16 bit number from location addr c addr display the 8 bit number fr...

Page 66: ...OpenBoot Firmware Base 520 G Installation Page 52 SPARC CPCI 52x G...

Page 67: ...O 52x G Installation Location Overview SPARC CPCI 52x G Page 53 5 I O 52x G Installation 5 1 Location Overview The I O 52x G contains the following main I O interfaces SCSI 2 Ethernet 2 PMC 1 and PMC...

Page 68: ...iagram of the I O 52x G schematic CPU and cache heatsink SCSI 2 Top APB Ethernet 2 PMC 2 connectors PHYceiver Front panel 1 slot high PMC 2 PMC 1 PMC 1 connectors Base 520 G connector P6 CPU and cache...

Page 69: ...following figures show the SPARC CPCI 52x G in 2 slot and 3 slot configurations Figure 17 Mechanical construction of the SPARC CPCI 522 Figure 18 Mechanical construction of the SPARC CPCI 52xG I O 52...

Page 70: ...pen end off the stand offs of the I O 52x G 3 Plug the I O 52x G to the Base 520 G via the I O 52x G to Base 520 G connector at position 7 and fix it with the 10 removed screws on the standoffs at loc...

Page 71: ...following table For a location diagram see figure 14 Location diagram of the I O board sche matic on page 47 2 1 3 4 6 CPU and cache heatsink SCSI Top APB Ethernet PMC 2 connectors PHYceiver PMC 1 co...

Page 72: ...via an MII 2 interface If Ethernet 2 gets accessed via I O panel the front panel connector is normally disabled automatically for other con figurations see the respective jumper settings in the SPARC...

Page 73: ...from being plugged into the PMC slots Connector Configuration The 32 bit PCI bus requires 2 PMC connectors The 3rd PMC connector PNx4 connects additional user I O signals of PMC slot 1 and PMC slot 2...

Page 74: ...C 2 I O 25 E PMC 1 I O 62 PMC 1 I O 57 PMC 1 I O 52 PMC 1 I O 47 PMC 1 I O 42 PMC 1 I O 37 PMC 1 I O 32 PMC 1 I O 27 PMC 1 I O 22 PMC 1 I O 17 PMC 1 I O 12 PMC 1 I O 7 PMC 1 I O 2 PMC 2 I O 62 PMC 2 I...

Page 75: ...panel supports the following interfaces Fast Wide SCSI 2 MII 2 Ethernet and PMC user I O Danger The SPARC IOBP 520 IO and the SPARC CPCI 520 AccKit IO is especially designed for the I O 52x G Do not u...

Page 76: ...always terminated at the SCSI 2 controller 5 6 Ethernet 2 Configuration Note Correct Ethernet selection The I O 52x G provides the following 2 Ethernet 2 interfaces via a TPE 2 interface connected to...

Page 77: ...cription Defined for SCSI 2 scsi 2 SCSI 2 disk26 disk SCSI 2 target ID 6 disk25 disk SCSI 2 target ID 5 disk24 disk SCSI 2 target ID 4 disk23 disk SCSI 2 target ID 3 disk22 disk SCSI 2 target ID 2 dis...

Page 78: ...OpenBoot Firmware Alias Definitions for I O 52x G I O 52x G Installation Page 64 SPARC CPCI 52x G...

Page 79: ...the PCIO PCI IO chip which interfaces to the local I O bus Described features of the Base 520 G The Base 520G is fully functional without the I O 52x G Besides the CompactPCI interface the SPARC CPCI...

Page 80: ...e Tx Ethernet 2 PMC slot 1 with 5V I O SCSI 1 SCSI 1 C o m p a c t P C I SCSI 2 XCVR Memory data Addr and ctrl Addr and ctrl Memory modules Ethernet 2 PHYceiver Keyboard mouse Keyboard mouse PCI bus A...

Page 81: ...ge 75 PCI A bus on Base 520 G little endian APB see page 75 CompactPCI interface see page 75 PCI bus B on Base 520 G little endian APB see page 75 Ethernet controller with EBus2 interface PCIO see pag...

Page 82: ...units 3 floating point execution units 2 graphics execution units Directly addresses little or big endian data 64 bit address pointers 16 KByte non blocking data cache 16 KByte instruction cache Integ...

Page 83: ...cheable 1FE 0000 000016 1FF FFFF FFFF16 8 GByte PCI noncacheable Table 30 UltraSPARC IIi internal CSR space 16 MByte Address range in PA 40 0 Size Description owner 1FE 0000 000016 1FE 0000 01FF16 512...

Page 84: ...ry interface is 72 bit wide 64 bits are shared with the UPA64S interface and 8 bits are used for ECC 6 bidi rectional registered multiplexers and demultiplexers XCVRs are used to extend the memory int...

Page 85: ...1 64 MByte 2 128 MByte 8M 8 1 256 MByte 2 MEM 50M or 50U 128 MByte 1 256 MByte 2 Table 32 Physical memory addresses for memory modules Physical address range Module number Bank Size in MByte Memory m...

Page 86: ...iority controlled Enabling interrupts Every interrupt routed to the UIC can be separately enabled or disabled in the interrupt source and in the processor The following table lists all interrupt sourc...

Page 87: ...internal priority Ethernet 2 PCIO 1516 0216 5 SCSI 2 SYM53C875 0516 0116 5 PMC1 A PMC1 0e16 1416 6 PMC1 B 0c16 1516 4 PMC1 C 0b16 1616 3 PMC1 D 0916 1716 1 PMC2 A PMC2 1616 1816 6 PMC2 B 1416 1916 4...

Page 88: ...35 UltraSPARC IIi PCI address space 8 GByte Address range in PA 40 0 Size Description Generated PCI commands 1FE 0000 000016 1FE 00FF FFFF16 16 MByte CPU internal CSR space n a 1FE 0100 000016 1FE 01...

Page 89: ...PCI bus B there are additional local PCI devices in both cases providing 2 PMC Slots with Busmode Support see page 98 SCSI 2 see section 6 4 SCSI Interface SYM53C875 on page 97 and Ethernet 2 see sect...

Page 90: ...zed via a PHYceiver device the PHYceiver ICS1890 It is directly connected to the MII interface of the PCIO The PHYceiver is a fully integrated physical layer device sup porting 10 and 100 Mbit s CSMA...

Page 91: ...ogic The resulting memory map in the PCI address space with the base address registers in the reset value con figuration is described in the table below After power up the Base 520 G PCIO is in boot m...

Page 92: ...Keyboard Mouse FDC and Parallel Interface Super I O on page 81 4 F140 000016 F14F FFFF16 Serial Interfaces SAB 82532 on page 80 5 F150 000016 F15F FFFF16 reserved 6 F160 000016 F16F FFFF16 System Conf...

Page 93: ...g to the assembled flash devices see section 6 3 10 SCR Boot and User Flash on page 89 The decoding is shown in the table below Table 39 Boot and user flash address space configuration PCI addr range...

Page 94: ...nd B They are implemented via the Enhanced Serial Communica tion Controller SAB 82532 User s Manual and Addendum at PCI bus base address F140 000016 on the EBus2 Device features 2 independent full dup...

Page 95: ...ompatibility see Parallel interface on page 82 Standard PC AT address decoding for all the on chip peripherals and a set of configuration registers are also implemented together with ad vanced power m...

Page 96: ...or bidirectional parallel interface Centronics compliant and operation in either programmed I O or DMA mode software or hardware control EPP Enhanced Parallel Port and ECP Enhanced Capabilities Port...

Page 97: ...e wide accessible real time clock and power fail control circuit for automatic power fail chip deselect and write protection Long life lithium carbon monofluoride battery Year 2000 compliant RTC with...

Page 98: ...ls on page 78 one for capture Micro In Line Aux In and one for playback Line Headphone Out Device features 16 bit stereo audio converters and complete on chip filtering for record and playback of 16 b...

Page 99: ...ee page 90 F160 000316 F016 I2C Bus Control and Status Register see page 96 F160 000416 F016 Miscellaneous Control Register see page 93 F160 000516 F016 Miscellaneous Control and Status Register see p...

Page 100: ...Display Control Register on page 87 SW4 and SW5 Status Register on page 89 BLINK_FREQ r w BLINK_FREQ specifies the blink frequency 002 no blinking 012 blinking at appr 0 5 Hz slow 102 blinking at app...

Page 101: ...re 24 Naming the parts of the 7 segment LED display ROTARY_SW ro ROTARY_SW indicates the current state of the rotary switch 00002 Rotary switch set to 016 00002 00012 Rotary switch set to 116 00012 00...

Page 102: ...Ethernet and EBus2 Devices PCIO Hardware Description Page 88 SPARC CPCI 52x G...

Page 103: ...ON 1 Switch is OFF SW5 2 ro SW5 2 indicates the setting of the SW5 2 SCSI Termination for SCSI 1 on P2 OFF backplane termination disabled see page 28 0 Switch is OFF 1 Switch is ON 6 3 10 SCR Boot and...

Page 104: ...tes its WDO output and a watchdog timer in terrupt can be generated if IE_WDT in the Watchdog and Temperature Control and Status Register is set appropriately The generation of an in terrupt is indica...

Page 105: ...perature sensor 1 or 2 0 default O S output signal is low 0 1 O S output signal is high 1 SW_PLCC_ TSOP r w SW_PLCC_TSOP controls the selection of the boot device the boot PROM or the boot flash EPROM...

Page 106: ...by WDT_RESET in the Reset Status Register 0 Interrupt generation disabled default after reset 1 Interrupt generation enabled IS_WDT ro IS_WDT indicates status of the WDO output signal and thereby indi...

Page 107: ...generated because the Com pactPCI reset signal has been asserted if BUS_RESET 1 WDT_RESET ro WDT_RESET indicates that a reset has been generated because of a watchdog timeout if WDT_RESET 1 RESET_STA...

Page 108: ...upt source by reading IP_ENUM1 and IP_ENUM2 IE_ENUMx r w IE_ENUMx specifies if the respective ENUM x interrupt is enabled x 1 or 2 Only if enabled an interrupt is generated to the processor in case of...

Page 109: ...ble below The ID PROMs are used to store board specific parameters The temper ature sensors can be programmed for temperature monitoring and protec tion against overheating To locate the temperature s...

Page 110: ...hat the read out of the data line via I2C_SDAI which immediately follows the setting of the SDA data line to the high level 1 strictly respects the 5 usec time constant before executing the read out O...

Page 111: ...and SCRIPTS instruction prefetch allowing tailored SCSI sequences to be executed locally SCRIPTS Symbios Logic developed SCSI programming language 536 byte DMA FIFO buffer allowing bursts of up to 12...

Page 112: ...e answer of PMC module x is transferred via PMC x BUSMODE 1 as described in table 58 PMC x BUSMODE 1 ro response encoding on page 99 Table 56 I O pins for PMC busmode function Busmode signal Pin name...

Page 113: ...x BUSMODE 1 ro response encoding PMC x BUSMODE 1 Description 0 Card Present PMC module present which has the requested capability and uses the requested protocol 1 no PMC module present or PMC module...

Page 114: ...PMC Slots with Busmode Support Hardware Description Page 100 SPARC CPCI 52x G...

Page 115: ...ual Set Besides the commands already provided by the standard OpenBoot firm ware the OpenBoot firmware available on the SPARC CPCI 52x G in cludes further words for accessing and configuring system sp...

Page 116: ...ns the contents an 8 bit data of the First User LED Control Register led1 ctrl byte stores the 8 bit data byte in the First User LED Control Register led2 ctrl byte returns the contents an 8 bit data...

Page 117: ...turns the state of the automatic Floppy Disk Eject Reg ister The floppy disk is ejected if true is returned eject_fd true false controls the automatic Floppy Disk Eject Register The floppy can be ejec...

Page 118: ...s pending if true is used with this com mand In that case an interrupt is generated to the processor provided that the SYSFAIL interrupt is enabled by the SYSFAIL Interrupt Enable Register This signal...

Page 119: ...vice MAX815 activates its WDO output and a Watchdog timer interrupt may be generated To start the watchdog timer it is necessary to trigger WDI once ie_temp true false returns the state of the Tempera...

Page 120: ...ermanently slow moderate and fast Example The following command makes the second user LED blink with a moderate frequency in red ok red moderate 1 led led on led turns on the user LED identified by le...

Page 121: ...ta i2 c slave addr transmits a byte data to the ID PROM which is identi fied by its i2c slave addr For i2c slave addr values see the select idprom description above addr specifies the offset within th...

Page 122: ...ensors Note All temperature values are measured in C and specified as degree degrees plus 1 10 degree 1 10 degrees cpu switch stat displays the current state of all switches on the SPARC CPCI 52x G ge...

Page 123: ...nd are modified using either the setenv or the set default command provided by OpenBoot The following NVRAM configuration variables are related to probing the PCI buses pcia probe list specifies the p...

Page 124: ...and program the on board flash EPROM flash messages vaddr returns the virtual address of the variable flash mes sages The state of this variable controls whether the words to erase and program the fla...

Page 125: ...addr to dest addr Use se lect flash to select the flash fill flash dest addr count pattern fills the selected flash EPROM beginning at dest addr with a particular pattern The number of Byte to be pro...

Page 126: ...tes 7 2 2 Flash EPROM Device Node The device tree of OpenBoot for the SPARC CPCI 52x G contains a de vice node associated with the user and boot flash EPROM The device alias flash is available as an a...

Page 127: ...EPROM and therefore are called bootflash The current state of the configuration parameters is displayed using printenv and is modified using either setenv or set default bootflash megs specifies the a...

Page 128: ...of offset is assigned to the internal position counter A subsequent access to the flash EPROM then starts at the adjusted offset After a successful seek error is 0 otherwise 1 is returned to indicate...

Page 129: ...e an image from the flash EPROM use the device alias flash together with the boot command ok boot flash Automatic loading The following NVRAM configuration parameters can be modified to de termine whe...

Page 130: ...ot flash EPROM There are 2 versions of this procedure The first version uses the OpenBoot command plcc2tsop which is available in OpenBoot versions 3 10 4 or greater whereas the second ver sion applie...

Page 131: ...any OpenBoot version In case of an OpenBoot version previous to 3 10 4 copy the OpenBoot image from the boot PROM into the boot flash EPROM as follows 1 Make sure to have the CPU board installed with...

Page 132: ...Boot contains commands to display all available drop in drivers to add them and to remove them Thus the drop in drivers can be loaded at any time to the OpenBoot image from net or other external media...

Page 133: ...UCT SERIAL NO DATE OF PURCHASE ORIGINATOR COMPANY POINT OF CONTACT TEL EXT ADDRESS PRESENT DATE AFFECTED PRODUCT HARDWARE SOFTWARE SYSTEMS AFFECTED DOCUMENTATION HARDWARE SOFTWARE SYSTEMS ERROR DESCRI...

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