-14- MBM-530NS User’s Manual
In addition to the advanced CPU features, the MediaGX processor integrates
a host of functions, which are typically implemented with external components.
A full-function graphics accelerator provides pixel processing and rendering
functions.
The NS MediaGX MMX-Enhanced Processor represents a new generation of
x86-compatible 64-bit microprocessors with sixth-generation features. The decoupled
load/store unit (within the memory management unit) allows multiple instructions in a
single clock cycle. Other features include single-cycle execution, single-cycle
instruction decode, 16KB write -back cache, and clock rates up to 300MHz.
These features are possible by the use of advanced-process technologies and
super pipelining.
1.2 DMA Controller
The equivalent of two 8237A DMA controllers are implemented on the
MBM-530NS board. Each controller is a four -channel DMA device that will
generate the memory addresses and control signals necessary to transfer
information directly between a peripheral device and memory. This allows high
speed information transfer with less CPU intervention. The two DMA
controllers are internally cascaded to provide four DMA channels for transfers
to 8-bit peripherals (DMA1) and three channels for transfers to 16-bit
peripherals (DMA2). DMA2 channel 0 provides the cascade interconnection
between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
The Following is the system information for the DMA channels:
Slave with four 8 -bit channels Master with three 16-bit
channels
DMA Controller 1
DMA Controller 2
Channel 0: Spare
Channel 4(0): Cascade for
controller 1
Channel 1: IBM SDLC
Channel 5(1): Spare
Channel 2: Diskette adapter
Channel 6(2): Spare
Channel 3: Spare
Channel 7(3): Spare
Summary of Contents for MBM-530NS
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