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Advanced Chipset Features
CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc.
Advanced Chipset Features
Northbridge Chipset Configuration
Help Item
► Memory Configuration
[Press Enter]
► DRAM Timing Configuration
[Press Enter]
CAS Latency
:5.0
RAS/CAS Delay
:5 CLK
Row Precharge Time
:5 CLK
Min Active RAS
:15 CLK
RAS/RAS Delay
:3 CLK
Row Cycle
:20 CLK
Internal Graphics Configuration
Internal Graphics Mode
[UMA]
UMA Frame Buffer Size
[Auto]
Primary Video Controller
[PCI-GFXO-IGFX]
Surround View
[Auto]
AMD 880 HD Audio
[Enabled]
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit
F1:General Help F9:Optimized Defaults
[Press Enter]
► Memory Configuration/DRAM Timing Configuration
Press <Enter> to go to its submenu.
The following six items display the DRAM timing values.
► CAS Latency
This item shows the CAS latency. The CAS Latency is the number of clock cycles that elapse
from the time the request for data is sent to the actual memory location until the data is
transmitted from the module.
► RAS / CAS Delay
This item displays a delay time (in clock cycles) between the CAS and RAS strobe
signals.
► Row Precharge Time
This item shows the number of clock cycles taken between issuing of the precharge command
and the active command. The DRAM row precharge time is in unit of clock cycle.
► Min Active RAS
Displays the number of clock cycles taken between a bank active command and
issuing of the precharge command.
► RAS / RAS Delay
This item shows a delay time (in clock cycles) between the RAS and RAS strobe
signals.
► Row Cycle
This item displays the minimum timing interval between successive active commands to the
same bank. The row cycle time is in unit of clock cycle.
► Internal Graphics Mode
Enable/Disable the integrated UMA graphics controller.
► UMA Frame Buffer Size
Allocates system memory for use as video memory to ensure the most efficient use of
available resources for maximum 2D/3D graphics performance.
This is a memory allocation method addition to the Unified Memory Architecture (UMA)
