Chapter 3 BIOS Description
26
DRAM Clock/Drive Control Menu
v
1T CMD Support
The item is used to select whether to support the first command latency of
one clock cycle.
v
Current FSB/DRAM Frequency
This item determines CAS Latency. The available setting values are: 3, 4, 5, 6
and Auto.
v
DRAM Clock
The item can be used to set the control mode of DRAM clock.
v
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to
“
Auto By SPD
”
enables DRAM tim-
ings to be determined by BIOS based on the configurations on the SPD.
Selecting
“
Manual
”
allows users to configure the DRAM timings manually.
The setting values are:Manual, Auto By SPD, Turbo, Ultra.
v
SDRAM CAS Latency [DDR/DDR2]
W hen synchronous SDRAM is installed, the number of clock cycles of CAS
latency depends on the SDRAM timing.
v
Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM. Dis-
able the function if 16MB SDRAM is installed.
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Summary of Contents for P4M8907SA
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