Freescale Semiconductor C29x, User Manual

Page 1: ...C29x PCIe Card User Guide Document Number C29xPCIeUG Rev 0 10 2013 ...

Page 2: ...C29x PCIe Card User Guide Rev 0 10 2013 2 Freescale Semiconductor Inc ...

Page 3: ...andalone Host Mode 14 2 3 PKCAL SKMM Mode 16 2 4 Secure Boot Mode 16 Chapter 3 Clocks Resets and Power Control 3 1 Clocks 19 3 2 Resets 20 3 3 Power Block Diagram 21 Chapter 4 On Board Resources 4 1 DDR Memories 23 4 2 IFC 24 4 2 1 NOR Flash Memory 24 4 2 2 NAND Flash Memory 25 4 3 SerDes 26 4 4 Ethernet 27 4 4 1 eTSEC1 27 4 4 2 eTSEC2 27 4 5 eSPI 28 C29x PCIe Card User Guide Rev 0 10 2013 Freesca...

Page 4: ...egister Definition 43 7 2 1 Chip ID1 Register CPLD_CHIPID1 44 7 2 2 Chip ID2 Register CPLD_CHIPID2 45 7 2 3 Hardware Version Register CPLD_HWVER 45 7 2 4 Software Version Register CPLD_SWVER 46 7 2 5 Reset Control Register CPLD_RSTCON 46 7 2 6 Flash Control and Status Register CPLD_FLHCSR 47 7 2 7 Watchdog Control and Status Register CPLD_WDCSR 48 7 2 8 Watchdog Kick Register CPLD_WDKICK 48 7 2 9 ...

Page 5: ...CFG1 51 7 2 14 Boot Configuration Register 2 CPLD_BOOTCFG2 51 7 2 15 Boot Configuration Register 3 CPLD_BOOTCFG3 52 7 2 16 Boot Configuration Register 4 CPLD_BOOTCFG4 53 Chapter 8 Programming U Boot 8 1 Programming U Boot on a Board having no U Boot Installed 55 C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 5 ...

Page 6: ...C29x PCIe Card User Guide Rev 0 10 2013 6 Freescale Semiconductor Inc ...

Page 7: ... Package ECC Elliptic Curve Cryptography EP Endpoint eTSEC Enhanced Three Speed Ethernet Controller I2C Inter Integrated Circuit IFC Integrated Flash Controller POR Power On Reset RC Root Complex RGMII Reduced Gigabit Media Independent Interface RMII Reduced Media Independent Interface RTS Ready To Send SerDes Serializer Deserializer SoC System On Chip SPI Serial Peripheral Interface UART Universa...

Page 8: ...performance security engine network and high speed serial interfaces DDR and non volatile memory controllers C29x Crypto Offload User Guide Explains the procedure to build configure and use different software components for the Freescale C29x crypto coprocessor device C29x PCIe Card Getting Started Guide Explains C29x PCIe board settings and physical connections needed to boot the board Freescale ...

Page 9: ...gnetics RS232 RJ45 Console RJ45 x2 Ethernet MDI RS232 XCVR UART GE PHY VSC8641 MDIO RGMII DUART RGMII C29x IFC I2C SerDes JTAG SPI COP Connector PCle x4 EEPROM S25FL 128 SPI IF I2C IF Thermal Monitor EEPROM AT24C1024 CORE POWER 12V PCle Finger Power Select Circuit 12V Power Jack Super Sequencer Power Regulators 1 0V Configs CPLD NAND Flash 4 GB NOR Flash 64 MB DDR3 512 MB 32 bit Reset Watch Dog GE...

Page 10: ...bit DDR3 memory of MT41J128M16 16 Mb SPI EEPROM of S25FL128 Power supplies External 12V DC power input 2x3 6 pin power connector for ATX power supply Headers Connector for ADM1069 power on control chipset programming Connector for CPLD programming Connector for ZL6105 digital power programming POR configuration Supports critical POR settings through DIP switches available on the board 1 4 Board Dr...

Page 11: ...easures 168 mm x 111 mm It can be installed into a PCIe x4 PCIe x8 or PCIe x16 slot on the PCIe motherboard The figure below shows the top view of the C29x PCIe card Chapter 1 Introduction C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 11 ...

Page 12: ... Gold finger ON OFF Switch Power LED UART ETH1 TSEC2 ETH0 TSEC1 J16 J15 DIP Switch J18 for Fan JTAG Figure 1 4 C29x PCIe card top view Board Drawing and Top View C29x PCIe Card User Guide Rev 0 10 2013 12 Freescale Semiconductor Inc ...

Page 13: ...9x PCIe card operating in the PCIe endpoint mode Figure 2 1 PCIe endpoint mode Perform the following steps to use the C29x PCIe card in the PCIe endpoint mode 1 Connect the heat sink fan power line to J18 2 Plug C29x PCIe into the PCIe slot on the motherboard C29x PCIe supports x1 x2 and x4 configurations C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 13 ...

Page 14: ...se by setting DIP switch SW7 1 ON cfg_cpu_boot 0 SW7 5 ON cfg_host_agt 0 The table below shows dual in line package DIP switch settings of the C29x PCIe card in PCIe endpoint mode 800 MHz core 400 MHz platform PCIe x4 configuration Table 2 1 PCIe endpoint mode DIP switch settings SW4 1 8 0101 1000 ON OFF ON OFF OFF ON ON ON SW5 1 8 1111 0000 OFF OFF OFF OFF ON ON ON ON SW6 1 8 0000 1111 ON ON ON O...

Page 15: ...umber of stop bits 1 Flow control Hardware None 6 Connect network cable to TSEC1 7 Turn on ON OFF switch to power on C29x PCIe Now you will see C29x PCIe boot up message on the computer console Following are the device configurations required for this use case by setting DIP switch SW7 1 OFF cfg_cpu_boot 1 The table below shows DIP switch settings of the C29x PCIe board in the standalone mode 800 ...

Page 16: ... The host can communicate with PCIe interface The PKCAL SKMM mode can be enabled by setting the SW8 8 switch To enable the PKCAL mode set SW8 8 to 0 To enable the SKMM mode set SW8 8 to 1 The PKCAL mode can be started from the PCIe endpoint mode In PKCAL mode a C29x processor only uses internal SDRAM instead of DDR3 NOR flash NAND flash Therefore DDR NOR flash NAND flash should not be initialized ...

Page 17: ... EEPROM To start the secure boot mode from the standalone host mode connect J16 pin 1 and pin 2 and install the battery The board will now support secure boot from NOR flash NAND flash or SPI EEPROM Following are the device configurations required for this use case by setting DIP switch SW7 6 ON cfg_sb_dis 0 The table below lists the secure boot POR settings example in NOR flash boot mode 800 MHz ...

Page 18: ...Secure Boot Mode C29x PCIe Card User Guide Rev 0 10 2013 18 Freescale Semiconductor Inc ...

Page 19: ...Chapter 3 Clocks Resets and Power Control 3 1 Clocks The figure below shows the C29x PCIe input clocks C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 19 ...

Page 20: ...B MCK LCK 0 1 10 MHz 100 MHz IFC SAP tck_nog tck PLL e500 Core Complex L2 idcp_ipg_clk div PLL SPI eSDHC I2C CAAMs Other IPs PCI EX div Figure 3 1 C29x PCIe input clocks In the above figure SYSCLK is a 66 67 MHz primary clock DDR_CLK is 100 MHz external clock SD_REFCLK is 100 MHz required for PCIe interface TSEC_RX_CLK is 125 MHz required for GE port CPLD_REFCLK is 32 768 kHz required for CPLD to ...

Page 21: ...k of C29x PCIe PS_RST_N ADM1069 Power Monitor GND Push Button MAX811S Power on RST PON_RST_N WD_CFG0 WDO N WDI MAX6370 Watch_Dog COP_ITF COP_SRST_N COP_HRST_N HRSET_N HRSET_REQ_N C29x AND CPLD Soft reset register AND GE2_RST_N GE2 PHY NOR FLASH DDR3 DDR3L WD_CFG1 WD_CFG2 GE1_RST_N AND GE1 PHY 7 6 5 4 3 2 1 0 Figure 3 2 C29x PCIe reset block 3 3 Power Block Diagram The figure below shows the power ...

Page 22: ...12V Ferrite Bead Ferrite Bead Ferrite Bead Filter GND GND GND 1V 1 5V 2 5V 12V 3V3 4A 1V0 GVDD 2V5 3V3 1V5 NCP571 SN10T1G 1V0 1V0_AVDD_DDR 1V0_AVDD_PLAT 1V0_SD_AVDD 1V0_SVDD 1V0_AVDD_CORE 1V0_LP LP_TMP_DET_N 1V5_XVDD GVDD 2V5 VTT MVREF 3V3 1V0_CA 1V0_CB VDDC VDD VDD_LL AVDD_DDR AVDD_CORE AVDD_PLAT AVDD_SD_PLL1 SVDD VDD_CA VDD_CB VDD_LP XVDD For C29x 2V5 LVDD 3V3 OVDD 02VDD BVDD CVDD GVDD Figure 3 ...

Page 23: ...3L memories The memory interface on the board is configured as DDR3 DDR3L The DDR3 DDR3L memory and ECC are implemented as a single bank discrete chipset x16 When DDR3 chipset is assembled the jumper J12 is connected to set the GVDD supply to 1 5V DC or is disconnected to set GVDD to 1 35V DC The memory size supported on the board is 512 MB 2 chips 2 Gbit chips 8bits The figure below shows the DDR...

Page 24: ...ss control and command signals are terminated to the VTT rail using a 40 2Ω resistor 4 2 IFC The C29x PCIe card supports the following two IFC resources NOR flash memory NAND flash memory 4 2 1 NOR Flash Memory The C29x PCIe card provides NOR flash memory of 64 MB with 16 bit port size The figure below shows the hardware connection between the C29x PCIe card and NOR flash memory IFC C29x PCIe Card...

Page 25: ...6 MB size each The DIP switch SW5 7 8 can be used to change the starting address for the memory banks Four different u boot images can be programmed into each memory bank When selecting NOR flash as boot flash CS0 is connected to NOR flash by setting SW5 6 to ON rom_location is set to 1111 using SW5 1 4 different u boot images can be selected to boot up the board by setting SW5 7 8 4 2 2 NAND Flas...

Page 26: ... On the C29x PCIe card the SerDes module implements link serialization deserialization and PCS functions for a PCI express link operating at 2 5 or 5 Gbaud The table below shows the different settings for SerDes Table 4 1 SerDes settings Functional signal Reset configuration name Value binary 4 lane Lynx 23 A B E F IFC_AD 13 14 IFC_BCTL Default 111 cfg_io_ports 0 2 000 PCIe x4 5 GHz 001 PCIe x4 2 ...

Page 27: ...faces are compliant with the PCI Express Base Specification Revision 2 0 which supports root complex RC and endpoint EP configurations 4 4 Ethernet The C29x PCIe card supports a maximum of two Ethernet ports 4 4 1 eTSEC1 eTSEC1 10 100 1000 BaseT operates in the RGMII mode and is directly connected to a Vitesse RGMII PHY VSC8641 as shown in the figure below C29x eTSEC1 RGMII MDC MDIO VSC8641 GBE PH...

Page 28: ... SPI standard A Spansion SPI flash memory is supported on the board 4 6 RS 232 The C29x processor has two UART controllers However due to space limitations the C29x PCIe card supplies only one RS 232 which provides an RS 232 standard interconnection between the board and an external host The serial connection is typically configured to run at 115 2 Kbps Each UART supports Full duplex operation Sof...

Page 29: ...e 4 6 RS 232 The table below shows the connection settings for the UART RJ45 to DB9 female cable connections Table 4 2 RJ45 to DB9 female connection settings RJ45 pin number RS 232 signal DB9 female pin number 1 RTS 8 2 NC 3 TXD 2 4 GND 5 GND 5 6 RXD 3 7 NC 8 CTS 7 Before powering up the C29x PCIe card configure the serial port of the attached computer with the following values Data rate 115200 bp...

Page 30: ... Number of data bits 8 Parity None Number of stop bits 1 Flow control Hardware None RS 232 C29x PCIe Card User Guide Rev 0 10 2013 30 Freescale Semiconductor Inc ...

Page 31: ...all header connectors on the C29x PCIe card Table 5 2 Header settings Reference designator Description Notes J3 JTAG COP connector Used for PowerPC JTAG J10 ZL6105 program port Digital power chipset ZL6105 I2C interface for programming J17 ADM1069 program port Power on control and power monitor chipset ADM1069 program port J18 Fan port Fan power supply 12V DC and speed control interface J9 CPLD he...

Page 32: ...appropriate header connector COP is a part of the C29x s JTAG module and is implemented as a set of additional instructions and logic This port can connect to a dedicated emulator for extensive system debugging Several third party emulators available in the market can connect to the host computer using the Ethernet port USB port parallel port RS 232 and so on The figure below shows a typical setup...

Page 33: ...sor and JTAG COP connector 8 CKSTP_IN Connected directly between the processor and JTAG COP connector 9 TMS Connected directly between the processor and JTAG COP connector 10 NC Not connected 11 SRESET Routed to the RESET PLD SRESET to the processor is generated from the PLD 12 GND Connected to ground 13 HRESET Routed to the RESET PLD HRESET to the processor is generated from the PLD 14 KEY Not co...

Page 34: ...eference designator Used for Notes Flash green Software boot is ok 5 6 Push Button The push button SW1 on the C29x PCIe card is used for reset Push Button C29x PCIe Card User Guide Rev 0 10 2013 34 Freescale Semiconductor Inc ...

Page 35: ...ency is at or below 66 MHz 1 SYSCLK frequency is above 66 MHz SW4 5 cfg_core_pll 0 IFC_AD3 OFF Ratio between the e500 core clock and e500 CCB clock SW4 5 6 7 ON ON ON 000 reserved SW4 5 6 7 ON ON OFF 001 reserved SW4 5 6 7 ON OFF ON 010 1 1 SW4 5 6 7 ON OFF OFF 011 1 5 1 SW4 5 6 7 OFF ON ON 100 2 1 SW4 5 6 7 OFF ON OFF 101 2 5 1 SW4 5 6 7 OFF OFF ON 110 3 1 SW4 5 6 7 OFF OFF OFF 111 3 5 1 SW4 6 cf...

Page 36: ...0 1 select ON 0 CS0 is connected to NOR flash CS1 is connect to NAND flash OFF 1 CS0 is connected to NAND flash CS1 is connected to NOR flash SW5 7 FBANK_SEL1 ON NOR boot section choose Set which section works as a boot section SW5 8 FBANK_SEL2 ON SW6 1 cfg_ddr_pll 0 SW_TSEC1_TXD 0 ON Clock ratio between 100Mhz OSC clock input and DDR complex clock SW6 1 2 3 ON ON ON 000 8 1 SW6 1 2 3 ON ON OFF 00...

Page 37: ...uration information from a ROM on the I2C1 interface A valid ROM must be present SW6 7 8 OFF ON 10 Extended I2C addressing mode is used Boot sequencer is enabled and loads configuration information from a ROM on the I2C1 interface A valid ROM must be present SW6 7 8 OFF OFF 11 Boot sequencer is disabled No I2C ROM is accessed This is the default setting SW6 8 cfg_boot_seq 1 IFC_A19 OFF SW7 1 cfg_c...

Page 38: ...ector to be placed in GPPORCR Software can then use this value to inform the operating system about initial system configuration Typical interpretations include circuit board type board ID number or a list of available peripherals SW8 2 cfg_gpinput 1 IFC_WE_N ON SW8 3 cfg_gpinput 2 IFC_CLE ON SW8 4 cfg_gpinput 3 UART0_TXD ON SW8 5 cfg_eng_use 0 SW_EC_MDC OFF To be used in the future to control fun...

Page 39: ...ction mode if NAND flash is used for booting 00 4b correction per 520 Byte sector 01 8b correction per 520 Byte sector 10 24b correction per 520 Byte sector 11 40b correction per 520 Byte sector R274 cfg_ifc_ecc_mode 1 IFC_A27 NC 1 R275 cfg_ifc_ecc_dec_en IFC_A21 4 7k 0 Enable IFC ECC checking on boot if NAND flash is used for booting 0 ECC decoding disabled 1 ECC decoding enabled R276 cfg_ifc_fla...

Page 40: ...l UART1_TXD NC 1 Test port MUX select 0 Not selected 1 Selected R287 cfg_test_port_dis IFC_WP_N NC 1 Disable test port 1 Disabled 0 Enabled R289 cfg_60x TSEC2_TXD2 NC 1 R290 cfg_pcc_drowsy_en IFC_A20 4 7k 0 Enable PPC drowsy 0 Disabled 1 Enabled R425 cfg_sdram_drawsy_en IRQ_OUT_N 4 7k 0 Enable SDRAM drowsy 0 Disabled 1 Enabled In the above tables ON indicates 0 and OFF indicates 1 6 1 POR Settings...

Page 41: ...he table below shows POR settings in NOR flash boot mode 1200 MHz core 800 MHz DDR PCIe x4 agent Table 6 5 NOR flash POR settings for 1200 MHz core SW4 1 8 0101 1101 ON OFF ON OFF OFF OFF ON OFF SW5 1 8 1111 0000 OFF OFF OFF OFF ON ON ON ON SW6 1 8 0000 1111 ON ON ON ON OFF OFF OFF OFF SW7 1 8 1001 0111 OFF ON ON OFF ON OFF OFF OFF SW8 1 8 0000 1011 ON ON ON ON OFF ON OFF OFF NOR flash POR DIP set...

Page 42: ...ngs The table below shows POR settings in SPI flash boot mode 800 MHz core 800 MHz DDR PCIe x4 agent Table 6 7 SPI flash POR settings SW4 1 8 0101 1000 ON OFF ON OFF OFF ON ON ON SW5 1 8 0110 0100 ON OFF OFF ON ON OFF ON ON SW6 1 8 0000 1111 ON ON ON ON OFF OFF OFF OFF SW7 1 8 1001 0111 OFF ON ON OFF ON OFF OFF OFF SW8 1 8 0000 1011 ON ON ON ON OFF ON OFF OFF SPI flash POR DIP setting SW5 1 4 0110...

Page 43: ...RST_N CPU reset by HRESET_REQ_N PEX_RESET Power monitor reset ADM1069 output Hardware watchdog timeout Generated reset signals DDR3_RST_N HRESET_N NOR_RST_N GE1_RST_N GE2_RST_N Revision logic 8 bit CPLD hardware revision and 8 bit CPLD software revision Hardware watchdog control Boot flash selection PKCAL SKMM mode selection Fan speed control POR control Register settings change critical POR value...

Page 44: ... 7 2 8 48 14 Fan Control and Status Register CPLD_FANCSR 8 R W 0Fh 7 2 9 49 15 Panel LED Control and Status Register CPLD_LEDCSR 8 R W 00h 7 2 10 49 16 Miscellanies Control and Status Register CPLD_MISCCSR 8 R W See section 7 2 11 50 17 Boot Configuration Override Register CPLD_BOOTOR 8 R W 00h 7 2 12 50 18 Boot Configuration Register 1 CPLD_BOOTCFG1 8 R W 00h 7 2 13 51 19 Boot Configuration Regis...

Page 45: ...3 Hardware Version Register CPLD_HWVER Address 0h base 2h offset 2h Bit 0 1 2 3 4 5 6 7 Read HW_VER Write Reset x x x x x x x x Notes x depends on actual board setting x Undefined at reset CPLD_HWVER field descriptions Field Description 0 7 HW_VER Hardware version The version field of the hardware board Chapter 7 CPLD Specification C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor In...

Page 46: ...4 5 6 7 Read GE2RST GE1RST Reserved SW_RST Write w1c w1c w1c Reset 0 0 0 0 0 0 0 0 CPLD_RSTCON field descriptions Field Description 0 GE2RST GE PHY2 reset Write 1 to clear 0 No reset occurs 1 GE PHY2 reset signal is produced 1 GE1RST GE PHY1 reset Write 1 to clear 0 No reset occurs 1 GE PHY1 reset signal is produced 2 6 This field is reserved Reserved 7 SW_RST Software reset Write 1 to clear 0 No ...

Page 47: ...0 NOR flash bank select bit 1 is 0 1 NOR flash bank select bit 1 is 1 2 SW_BANK_SEL2 0 NOR flash bank select bit 2 of switch status is 0 1 NOR flash bank select bit 2 of switch status is 1 3 SW_BANK_SEL1 0 NOR flash bank select bit 1 of switch status is 0 1 NOR flash bank select bit 1 of switch status is 1 4 5 This field is reserved Reserved 6 BANK_OR Bank override 0 NOR flash bank select from CPL...

Page 48: ...0 Watchdog timeout is 30 ms 011 Watchdog timeout is disabled 100 Watchdog timeout is 100 ms 101 Watchdog timeout is 1 s 110 Watchdog timeout is 10 s 111 Watchdog timeout is 60 s 3 6 This field is reserved Reserved 7 WD_EN Watchdog enable 0 Watchdog is disabled 1 Watchdog is enabled 7 2 8 Watchdog Kick Register CPLD_WDKICK Address 0h base 13h offset 13h Bit 0 1 2 3 4 5 6 7 Read Write WD_KICK Reset ...

Page 49: ...an stops running 0001 1110 PWM duty cycle is 6 7 93 3 fan speed is in control 1111 PWM duty cycle is 0 fan is in full speed 4 7 This field is reserved Reserved 7 2 10 Panel LED Control and Status Register CPLD_LEDCSR Address 0h base 15h offset 15h Bit 0 1 2 3 4 5 6 7 Read LED Reserved Write Reset 0 0 0 0 0 0 0 0 CPLD_LEDCSR field descriptions Field Description 0 LED Light emitting device 0 Panel L...

Page 50: ...SEL_N 0 TEST_SEL_N pin status is 0 1 TEST_SEL_N pin status is 1 3 5 This field is reserved Reserved 6 PO2VDD_EN 0 PO2VDD power is disabled 1 PO2VDD power is enabled 7 PO1VDD_EN 0 PO1VDD power is disabled 1 PO1VDD power is enabled 7 2 12 Boot Configuration Override Register CPLD_BOOTOR Address 0h base 17h offset 17h Bit 0 1 2 3 4 5 6 7 Read BOOT_OR Reserved Write Reset 0 0 0 0 0 0 0 0 CPLD_BOOTOR f...

Page 51: ...peed Configuration core speed 1 3 cfg_core_pll 0 2 Configuration core PLL 4 cfg_sys_speed Configuration system speed 5 7 cfg_sys_pll 0 2 Configuration system PLL 7 2 14 Boot Configuration Register 2 CPLD_BOOTCFG2 NOTE For more information on BOOTCFG2 register refer to C29x datasheet Address 0h base 19h offset 19h Bit 0 1 2 3 4 5 6 7 Read cfg_boot_seq 0 1 cfg_plat_ speed cfg_ddr_speed 0 1 cfg_ddr_p...

Page 52: ...ore information on BOOTCFG3 register refer to C29x datasheet Address 0h base 1Ah offset 1Ah Bit 0 1 2 3 4 5 6 7 Read cfg_svr 0 1 cfg_sb_dis cfg_rom_loc 0 3 cfg_cpu_ boot Write Reset 0 0 0 0 0 0 0 0 CPLD_BOOTCFG3 field descriptions Field Description 0 1 cfg_svr 0 1 2 cfg_sb_dis 3 6 cfg_rom_loc 0 3 Configuration ROM location 7 cfg_cpu_boot Configuration CPU boot CPLD Memory Map Register Definition C...

Page 53: ...e 1Bh offset 1Bh Bit 0 1 2 3 4 5 6 7 Read Reserved cfg_eng_use 0 1 cfg_gpinput 0 3 Write Reset 0 0 0 0 0 0 0 0 CPLD_BOOTCFG4 field descriptions Field Description 0 1 This field is reserved Reserved 2 3 cfg_eng_use 0 1 4 7 cfg_gpinput 0 3 Chapter 7 CPLD Specification C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 53 ...

Page 54: ...CPLD Memory Map Register Definition C29x PCIe Card User Guide Rev 0 10 2013 54 Freescale Semiconductor Inc ...

Page 55: ...lable on C29x PCIe DVD to 0x10FFFC00 9 Set the computer to 0x1107f000 and run When u boot outputs message on console enter u boot environment 10 Set u boot variables such as ipaddr serverip ethaddr and eth1addr 11 Perform one of the following steps to program NOR NAND SPI u boot a Use the following commands to program NOR u boot tftp 1000000 u boot bin protect off all erase fff80000 ffffffff cp b ...

Page 56: ...Programming U Boot on a Board having no U Boot Installed C29x PCIe Card User Guide Rev 0 10 2013 56 Freescale Semiconductor Inc ...

Page 57: ...R0 0x40800000 reg SPR_GROUP DBCR1 0x00000000 Run the core config runcontrolsync off go wait 50 config runcontrolsync on stop Clear affected registers reg SPR_GROUP DBSR 0x01CF0000 reg SPR_GROUP DBCR0 0x41000000 reg SPR_GROUP IAC1 0x00000000 reg SPR_GROUP CSRR0 0x00000000 reg SPR_GROUP CSRR1 0x00000000 proc init_P1010 global CCSRBAR variable SPR_GROUP e500 Special Purpose Registers variable SPR e50...

Page 58: ...0000000 delete CAM11 reg CAM_GROUP L2MMU_CAM11 0x00000000000000000000000000000000 delete CAM12 reg CAM_GROUP L2MMU_CAM12 0x00000000000000000000000000000000 delete CAM13 reg CAM_GROUP L2MMU_CAM13 0x00000000000000000000000000000000 delete CAM14 reg CAM_GROUP L2MMU_CAM14 0x00000000000000000000000000000000 delete CAM15 reg CAM_GROUP L2MMU_CAM15 0x00000000000000000000000000000000 disable invalidate all...

Page 59: ..._MODE_2 mem CCSR 0x211C 0x00000000 DDR_SDRAM_MD_CNTL mem CCSR 0x2120 0x00000000 DDR_SDRAM_INTERVAL mem CCSR 0x2124 0x0a280000 DDR_DATA_INIT mem CCSR 0x2128 0xDEADBEEF DDR_SDRAM_CLK_CNTL mem CCSR 0x2130 0x03000000 TIMING_CFG_4 mem CCSR 0x2160 0x00000001 TIMING_CFG_5 mem CCSR 0x2164 0x03402400 DDR_ZQ_CNTL mem CCSR 0x2170 0x89080600 DDR_WRLVL_CNTL mem CCSR 0x2174 0x8655a608 ERR_INT_EN mem CCSR 0x2E48...

Page 60: ...5 0x00000600 IVOR6 program reg SPR IVOR6 0x00000700 IVOR8 system call reg SPR IVOR8 0x00000c00 IVOR10 decrementer reg SPR IVOR10 0x00000900 IVOR11 fixed interval timer interrupt reg SPR IVOR11 0x00000f00 IVOR12 watchdog timer interrupt reg SPR IVOR12 0x00000b00 IVOR13 data TLB errror reg SPR IVOR13 0x00001100 IVOR14 instruction TLB error reg SPR IVOR14 0x00001000 IVOR15 debug reg SPR IVOR15 0x0000...

Page 61: ...rting at program entry point when stack is not initialized reg GPRS SP 0x0000000F proc envsetup Environment Setup radix x config hexprefix 0x config MemIdentifier v config MemWidth 32 config MemAccess 32 config MemSwap off Main envsetup init_P1010 C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 61 ...

Page 62: ...C29x PCIe Card User Guide Rev 0 10 2013 62 Freescale Semiconductor Inc ...

Page 63: ...ble below provides revision history of this document Table B 1 Document revision history Revision number Date Change description Rev 0 10 2013 Initial public release C29x PCIe Card User Guide Rev 0 10 2013 Freescale Semiconductor Inc 63 ...

Page 64: ...C29x PCIe Card User Guide Rev 0 10 2013 64 Freescale Semiconductor Inc ...

Page 65: ...eters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursua...