HOST INTERFACE (HI)
5 - 14
PORT B
MOTOROLA
of the HI visible to the DSP CPU. The effects of the different types of reset on these reg-
isters are shown. A brief discussion of interrupts and operation of the DSP side of the HI
complete the programming model from the DSP viewpoint. The programming model from
the host viewpoint begins at
Section 5.3.3.1 Programming Model – Host Processor
5.3.2.1
Host Control Register (HCR)
The HCR is an 8-bit read/write control register used by the DSP to control the HI interrupts
and flags. The HCR cannot be accessed by the host processor. It occupies the low-order
byte of the internal data bus; the high-order portion is zero filled. Any reserved bits are
read as zeros and should be programmed as zeros for future compatibility. (The bit manip-
ulation instructions are useful for accessing the individual bits in the HCR.) The contents
of the HCR are cleared on hardware or software reset. The control bits are described in
the following paragraphs.
5.3.2.1.1
HCR Host Receive Interrupt Enable (HRIE) Bit 0
The HRIE bit is used to enable a DSP interrupt when the host receive data full (HRDF)
status bit in the host status register (HSR) is set. When HRIE is cleared, HRDF interrupts
are disabled. When HRIE is set, a host receive data interrupt request will occur if HRDF
is also set. Hardware and software resets clear HRIE.
5.3.2.1.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit is used to enable a DSP interrupt when the host transmit data empty
(HTDE) status bit in the HSR is set. When HTIE is cleared, HTDE interrupts are disabled.
When HTIE is set, a host transmit data interrupt request will occur if HTDE is also set.
Hardware and software resets clear the HTIE.
5.3.2.1.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit is used to enable a vectored DSP interrupt when the host command pend-
ing (HCP) status bit in the HSR is set. When HCIE is cleared, HCP interrupts are dis-
abled. When HCIE is set, a host command interrupt request will occur if HCP is also set.
The starting address of this interrupt is determined by the host vector (HV). Hardware
and software resets clear the HCIE.
5.3.2.1.4
HCR Host Flag 2 (HF2) Bit 3
The HF2 bit is used as a general-purpose flag for DSP-to-host communication. HF2 may
be set or cleared by the DSP. HF2 is visible in the interrupt status register (ISR) on the
host processor side (see Figure 5-10). Hardware and software resets clear HF2.
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