HOST INTERFACE (HI)
MOTOROLA
PORT B
5 - 41
The previous transfer description is an overview. Specific and exact information for the HI
data transfers and their timing can be found in Section 5.3.6.3 DMA Data Transfer and
in the DSP56002 Advance Information Data Sheet (DSP56002/D).
5.3.6.2.1
Host to DSP - Data Transfer
Figure 5-23 shows the bits in the ISR and ICR registers used by the host processor and the
bits in the HSR and HCR registers used by the DSP to transfer data from the host processor to
the DSP. The registers shown are the status register and control register as they are seen by
the host processor, and the status register and control register as they are seen by the DSP.
Only the registers used to transmit data from the host processor to the DSP are
STEP 2 OF HOST PORT CONFIGURATION
1. CLEAR HOST COMMAND BIT (HC):
BIT 7 = 0
$1
7
6
5
0
HC
HV
2. OPTION 1: SELECT HOST VECTOR (HV)
(OPTIONAL SINCE HV CAN BE SET ANY TIME BEFORE THE HOST COMMAND IS EXECUTED. DSP INTERRUPT VECTOR = THE HOST
VECTOR MULTIPLIED BY 2. DEFAULT (UPON DSP RESET): HV = $12
➞
DSP INTERRUPT VECTOR $0024
*
*
Reserved; write as zero.
COMMAND VECTOR REGISTER (CVR)
(READ/WRITE)
Figure 5-21 (a) HI Configuration–Host Side
INIT
HM1
HM0
HF1
HF0
TREQ RREQ
$0
*
Reserved; write as zero.
STEP 2 OF HOST PORT CONFIGURATION
2. OPTION 2: SELECT POLLING MODE FOR HOST TO DSP COMMUNICATION
7
6
5
4
3
2
1
0
INITIALIZE DSP
AND HOST PORT
DMA OFF
BIT 5 = 0
BIT 6 = 0
OPTIONAL
DISABLE INTERRUPTS
BIT 0 = 0
BIT 1 = 0
INTERRUPT CONTROL REGISTER (ICR)
(READ/WRITE)
*
Figure 5-21 (b) HI Initialization–Host Side, Polling Mode
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..