HOST INTERFACE (HI)
5 - 44
PORT B
MOTOROLA
The receive routine in Figure 5-26 was implemented as a long interrupt (the instruction at
the interrupt vector location, which is not shown, is a JSR). Since there is only one instruc-
tion, this could have been implemented as a fast interrupt. The MOVEP instruction moves
data from the HI to a buffer area in memory and increments the buffer pointer so that the
next word received will be put in the next sequential location.
5.3.6.2.2
Host to DSP – Command Vector
The host processor can cause three types of interrupts in the DSP (see Figure 5-27).
These are host receive data (P:$0020), host transmit data (P:$0022), and host command
(P:$0024 - P:$007E). The host command (HC) can be used to control the DSP by forcing
it to execute any of 45 subroutines that can be used to run tests, transfer data, process
data, etc. In addition, the HC can cause any of the other 19 interrupt routines in the DSP
to be executed.
The process to execute a HC (see Figure 5-28) is as follows:
TREQ
RREQ
INIT Execution
0
0
INIT = 0; Address Counter = 00
0
1
INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = 00
1
0
INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = 00
INIT
HM1
HM0
HF1
HF0
0
TREQ
RREQ
HOST SETS INIT BIT
7
0
INTERRUPT CONTROL REGISTER (ICR)
(READ/WRITE)
MODES
0
0
Interrupt Mode (DMA Off)
0
1
24 Bit DMA Mode
1
0
16 Bit DMA Mode
1
1
8 Bit DMA Mode
RESET CONDITION
INTERRUPT MODE (DMA OFF)
TREQ
RREQ
INIT Execution
0
0
INIT = 0; Address Counter = HM1, HM0
0
1
INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = HM1, HM0
1
0
INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = HM1, HM0
1
1
Undefined (Illegal)
DMA MODE
INIT is used by the HOST to force initialization of the HI hardware.
The HI hardware automatically clears INIT when the command is executed.
INIT is cleared by DSP RESET.
Figure 5-22 Host Mode and INIT Bits
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Freescale Semiconductor, Inc.
For More Information On This Product,
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