SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 25
5.
The transmit data on the TXD pin changes on the negative edge of the 1
×
serial clock and is stable on the positive edge (SCKP=0). For SCKP equals
one, the data changes on the positive edge and is stable on the negative
edge.
6.
The receive data on the RXD pin is sampled on the positive edge (if SCKP=0)
or on the negative edge (if SCKP=1) of the 1
×
serial clock.
7.
For the asynchronous mode, the output clock is continuous.
8.
For the synchronous mode, a 1
×
clock is used for the output or input baud
rate. The maximum 1
×
clock is the crystal frequency divided by 8.
9.
For the synchronous mode, the clock is gated.
10.
For both the asynchronous and synchronous modes, the transmitter and
receiver are synchronous with each other.
6.3.2.3.1
SCCR Clock Divider (CD11–CD0) Bits 11–0
The clock divider bits (CD11–CD0) are used to preset a 12-bit counter, which is decre-
mented at the I
cyc
rate (crystal frequency divided by 2). The counter is not accessible to
the user. When the counter reaches zero, it is reloaded from the clock divider bits. Thus,
a value of 0000 0000 0000 in CD11–CD0 produces the maximum rate of I
cyc
, and a value
of 0000 0000 0001 produces a rate of I
cyc
/2. The lowest rate available is I
cyc
6-12 and Figure 6-35 show the clock dividers. Bits CD11–CD0 are cleared by hardware
and software reset.
RX, TX DATA
(SSFTD = 0)
IDLE LINE
START
STOP START
0
1
2
3
4
5
6
7
8
SELECT 8-OR 9-BIT WORDS
x1 CLOCK
x16 CLOCK
(SCKP = 0)
Figure 6-11 16 x Serial Clock
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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