SERIAL COMMUNICATION INTERFACE (SCI)
6 - 32
PORT C
MOTOROLA
Table 6-3 (a) through Table 6-4 (b) provide the settings for common baud rates for
Register
Bit
Bit
Mnemonic
Bit Number
Reset Type
HW Reset
SW Reset
IR Reset
ST Reset
SCKP
15
0
0
–
–
STIR
14
0
0
–
–
TMIE
13
0
0
–
–
TIE
12
0
0
–
–
RIE
11
0
0
–
–
ILIE
10
0
0
–
–
TE
9
0
0
–
–
SCR
RE
8
0
0
–
–
WOMS
7
0
0
–
–
RWU
6
0
0
–
–
WAKE
5
0
0
–
–
SBK
4
0
0
–
–
SSFTD
3
0
0
–
–
WDS (2–0)
2–0
0
0
–
–
R8
7
0
0
0
0
FE
6
0
0
0
0
PE
5
0
0
0
0
SSR
OR
4
0
0
0
0
IDLE
3
0
0
0
0
RDRF
2
0
0
0
0
TDRE
1
1
1
1
1
TRNE
0
1
1
1
1
TCM
15
0
0
–
–
RCM
14
0
0
–
–
SCCR
SCP
13
0
0
–
–
COD
12
0
0
–
–
CD (11–0)
11–0
0
0
–
–
SRX
SRX (23–0)
23–16, 15–8, 7–0
–
–
–
–
STX
STX (23–0)
23–0
–
–
–
–
SRSH
SRS (8–0)
8–0
–
–
–
–
STSH
STS (8–0)
8–0
–
–
–
–
NOTES:
SRSH – SCI receive shift register, STSH – SCI transmit shift register
HW – Hardware reset is caused by asserting the external RESET pin.
SW – Software reset is caused by executing the RESET instruction.
IR – Individual reset is caused by clearing PCC (bits 0–2) (configured for general-purpose I/O).
ST – Stop reset is caused by executing the STOP instruction.
1 – The bit is set during the xx reset.
0 – The bit is cleared during the xx reset.
– – The bit is not changed during the xx reset.
Table 6-2 SCI Registers after Reset
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