SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 43
rupt vector location, sets the memory wait states to zero, and configures the memory
SERIAL
CLOCK
(INT)
STX
WRITE
RANGE
FIRST W
ORD
NO
TE:
In inter
nal cloc
k mode
, if data 2 is wr
itten after the middle of bit 6 of data 1, then a gap of at least tw
o ser
ial bits is inser
ted
betw
een w
ord 1 and w
ord 2.
The gap is bigger as STX is wr
itten later
.
SYNCHR
ONOUS MODE, INTERNAL CLOCK (MASTER)
STX WRITE
RANGE
MAX 5.5 SERIAL CLOCK CYCLES
STX
WRITE RANGE FOR NO
GAP BETWEEN
W
ORDS 1 AND 2
TRDE
TDRE
0 BY STX
WRITE
TXD
(TRANS-
MIT D
A
TA
)
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
SECOND W
ORD
SERIAL
CLOCK
(EXT)
STX
WRITE
RANGE
FIRST W
ORD
NO
TE:
In e
xter
nal cloc
k mode
, if data 2 is wr
itten after the middle of bit 6 of data 1, then the pre
vious data is retr
ansmitted and
data 2 is tr
ansmitted after the retr
ansmission of data 1.
SYNCHR
ONOUS MODE, INTERNAL CLOCK (SLA
VE)
STX WRITE
RANGE
TRDE
TDRE
0 BY STX
WRITE
TXD
(TRANS-
MIT D
A
TA
)
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
SECOND W
ORD
STX WRITE
RANGE
Figure 6-19 Synchronous Timing
(a) Master
(b) Slave
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
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