SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 61
interrupt is recognized (5), SRIINT is automatically cleared, and the SCI waits for the first
start bit of the next character. Since RIE was set, when the first character is received, an
SCI receive data interrupt (or SCI receive data with exception status interrupt if an error
is detected) will be recognized as pending. When the receiver has processed the mes-
sage and is ready to wait for another idle line, RWU must be set to one again.
6.3.8.4
Address Mode Wakeup
The purpose and basic operational procedure for address mode wakeup is the same as
idle line wakeup. The difference is that address mode wakeup re-enables the SCI when
the ninth bit in a character is set to one (if cleared, this bit marks a character as data; if
set, an address). As a result, an idle line is not needed, which eliminates the dead time
between messages. If the protocol is such that the address byte is not needed or is not
wanted in the first byte of the message, a data byte can be written to STXA at the begin-
ning of each message. It is not essential that the first byte of the message contain an ad-
dress; it is essential that the start of a new message is indicated by setting the ninth bit to
one using STXA.
Figure 6-33 shows how to configure the SCI to detect and respond to an address charac-
ter. The word format chosen (WDS2, WDS1, and WDS0 in the SCR) must be an asyn-
chronous word format. The WAKE bit must be set to select address mode wakeup and
RWU must be set to put the SCI to “sleep” and enable the wakeup function. RIE should
be set if interrupts are to be used to receive data. (1) When an address character (ninth
bit=1) is received, then R8 is set to one in the SSR, and RWU is cleared. Clearing RWU
re-enables the SCI receiver. Since (2) RIE was set in this example, when the first charac-
ter is received, an SCI receive data interrupt (or SCI receive data with exception status
interrupt if an error is detected) will be recognized as pending. When the receiver is ready
to wait for another address character, RWU must be set to one again.
6.3.8.5
Multidrop Example
The program shown in Figure 6-34 configures the SCI as a multidrop master transmitter
and slave receiver (using wakeup on address bit) that uses interrupts to transmit data from
a circular buffer and to receive data into a different circular buffer. This program can be run
with the I/O pins (RXD and TXD) connected and with a pullup resistor for test purposes.
The program starts by setting equates for convenience and clarity and then points
the reset vector to the start of the program. The receive and transmit interrupt vec-
tor locations have JSRs forming long interrupts because the multidrop protocol and
circular buffers require more than two instructions for maintenance. Byte packing
and unpacking are not used in this example. The SRX and STX registers are equat-
ed to $FFF4, causing only the LSB of the 24-bit DSP word to be used for SCI data.
The SCI is then initialized as wired-OR, multidrop, and using interrupts. The SCI
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