SYNCHRONOUS SERIAL INTERFACE (SSI)
MOTOROLA
PORT C
6 - 89
(SCD1) bit is set, indicating that the SC1 pin is an output, then data present in OF1 will be
written to the SC1 pin at the beginning of the frame in normal mode or at the beginning of
the next time slot in network mode (see 6.4.7).
The normal sequence for setting output flags when transmitting data is to poll TDE (TX
empty), to first write the flags, and then write the transmit data to the TX register. OF0 and
OF1 are double buffered so that the flag states appear on the pins when the TX data is
transferred to the transmit shift register (i.e., the flags are synchronous with the data).
Hardware and software reset clear OF1.
Note: The optional serial output pins (SC0, SC1, and SC2) are controlled by the frame
timing and are not affected by TE or RE.
6.4.2.2.3
CRB Serial Control 0 Direction (SCD0) Bit 2
SCD0 controls the direction of the SC0 I/O line. When SCD0 is cleared, SC0 is an input;
when SCD0 is set, SC0 is an output (see Tables Table 6-5 and Table 6-6, and Figure
6-46). Hardware and software reset clear SCD0.
6.4.2.2.4
CRB Serial Control 1 Direction (SCD1) Bit 3
SCD1 controls the direction of the SC1 I/O line. When SCD1 is cleared, SC1 is an input;
when SCD1 is set, SC1 is an output (see Tables Table 6-5 and Table 6-6 and Figure
6-46). Hardware and software reset clear SCD1.
6.4.2.2.5
CRB Serial Control 2 Direction (SCD2) Bit 4
SCD2 controls the direction of the SC2 I/O line. When SCD2 is cleared, SC2 is an input;
when SCD2 is set, SC2 is an output (see Tables Table 6-5 and Table 6-6, and Figure
6-46). Hardware and software reset clear SCD2.
6.4.2.2.6
CRB Clock Source Direction (SCKD) Bit 5
SCKD selects the source of the clock signal used to clock the transmit shift register in the
asynchronous mode and both the transmit shift register and the receive shift register in
the synchronous mode. When SCKD is set, the internal clock source becomes the bit
clock for the transmit shift register and word length divider and is the output on the SCK
pin. When SCKD is cleared, the clock source is external; the internal clock generator is
disconnected from the SCK pin, and an external clock source may drive this pin. Hard-
ware and software reset clear SCKD.
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Freescale Semiconductor, Inc.
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