TIMER CONTROL/STATUS REGISTER (TCSR)
MOTOROLA
DSP56002 TIMER AND EVENT COUNTER
7 - 5
the signal coming in on the TIO pin, depending on the timer mode. See
Sections
for detailed descriptions of Timer Modes 4 and 5.
7.4
TIMER CONTROL/STATUS REGISTER (TCSR)
The 24-bit read/write TCSR controls the timer and verifies its status. The TCSR can be
accessed by normal move instructions and by bit manipulation instructions. The control
and status bits are described in the following paragraphs.
7.4.1
Timer Enable (TE) Bit 0
The TE bit enables or disables the timer. Setting the TE bit (TE=1) will enable the timer,
and the counter will be loaded with the value contained in the TCR and will start decre-
menting at each incoming event. Clearing the TE bit will disable the timer. Hardware
RESET and software RESET (RESET instruction) clear TE.
7.4.2
Timer Interrupt Enable (TIE) Bit 1
The TIE bit enables the timer interrupts after the counter reaches zero and a new event
occurs. If TCR is loaded with n, an interrupt will occur after (n+1) events.
Setting TIE (TIE=1) will enable the interrupts.When the bit is cleared (TIE=0) the interrupts
are disabled. Hardware and software resets clear TIE.
7.4.3
Inverter (INV) Bit 2
The INV bit affects the polarity of the external signal coming in on the TIO input and the
polarity of the output pulse generated on the TIO output.
If TIO is programmed as an input and INV=0, the 0-to-1 transitions on the TIO input pin
will decrement the counter. If INV=1, the 1-to-0 transitions on the TIO input pin will decre-
ment the counter.
If TIO is programmed as output and INV=1, the pulse generated by the timer will be in-
verted before it goes to the TIO output pin. If INV=0, the pulse is unaffected.
In Timer Mode 4 (see
Section 7.5.4 Timer Mode 4 (Pulse Width Measurement Mode)
the INV bit determines whether the high pulse or the low pulse is measured to determine
input pulse width. In Timer Mode 5 (see
Section 7.5.5 Timer Mode 5 (Period Measure-
), the INV bit determines whether the period is measured between leading or
trailing edges.
In GPIO mode, the INV bit determines whether the data read from or written to the TIO
pin shall be inverted (INV=1) or not (INV=0).
INV is cleared by hardware and software resets.
Note:
Because of its affect on signal polarity, and on how GPIO data is read and written,
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Freescale Semiconductor, Inc.
For More Information On This Product,
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