MOTOROLA
B - 19
Application:
Date:
Programmer:
Sheet 4 of 5
HOST
Interrupt Status Register (ISR)
$2 Read/Write
Reset = $06
4
3
2
1
0
HF3
HF2
TXDE RXDF
Transmit Data Register Empty
0 = Wait
1 = Write
Transmitter Ready
0 = Data in HI
1 = Data Not in HI
DMA Status
0 =
∏
DMA Disabled
1 =
∏
DMA Enabled
Host Flags
Read Only
Receive Data Register Full
0 = Wait
1 = Read
7
HREQ
6
5
*
0
PROCESSOR SIDE
DMA
TRDY
Host Request
0 =
∏
HREQ Deasserted1 =
∏
HREQ Asserted
Interrupt Vector Register (IVR)
$3 Read/Write
Reset = $0F
4
3
2
1
0
IV4
IV3
IV2
IV1
IV0
Exception vector number for use by MC68000
processor family vectored interrupts.
7
IV7
6
5
IV6
IV5
*
= Reserved, Program as zero
Figure B-20 Interrupt Status Register (ISR)
Figure B-21 Interrupt Vector Register (IVR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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