SIGNAL DESCRIPTIONS
2 - 6
DSP56002 PIN DESCRIPTIONS
MOTOROLA
2.2.2.8
Bus Grant (BG)
When this output is asserted, it signals to the external device that it has been granted the ex-
ternal bus (i.e. Port A has been three-stated).This output is deasserted during hardware reset.
2.2.2.9
Bus Strobe (BS)
The BS output is asserted when the DSP accesses Port A. It acts as an early indication
of the state of the external bus access by the DSP56002. It may also be used with the bus
wait input, WT, to generate wait states, a feature which provides capabilities such as con-
necting asynchronous devices to the DSP, allowing devices with differing timing
requirements to reside in the same memory space, allowing a bus arbiter to provide a fast
multiprocessor bus access, and providing an alternative to the WAIT and STOP instruc-
tions to halt the DSP at a known program location and have a fast restart. This output is
deasserted during hardware reset.
2.2.2.10
Bus Wait (WT)
For as long as it is asserted by an external device, this input allows that device to force
the DSP56002 to generate wait states. If WT is asserted when BS is asserted, wait states
will be inserted into the current cycle (see the
DSP56002 Technical Data Sheet
(DSP56002/D) for timing details.
2.2.3
Interrupt and Mode Control
The interrupt and mode control pins select the chip’s operating mode as it comes out of
hardware reset, and they receive interrupt requests from external sources.
2.2.3.1
Mode Select A/External Interrupt Request A (MODA/IRQA)/STOP Recovery
This input pin has three functions. It works with the MODB and MODC pins to select the
chip’s operating mode, it receives an interrupt request from an external source, and it
turns on the internal clock generator, causing the chip to recover from the stop processing
state. Reset causes this input to act as MODA.
During reset, this pin should be forced to the desired state, because as the chip comes
out of reset, it reads the states of MODA, MODB, and MODC and writes the information
to the Operating Mode Register to set the chip’s operating mode. (Operating Modes are
discussed in
SECTION 3 MEMORY MODULES AND OPERATING MODES
.) After the
chip has left the reset state, the MODA pin automatically changes to external interrupt
request IRQA.
IRQA receives external interrupt requests. It can be programmed to be level sensitive or
negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage
level and is not directly related to the fall time of the interrupt signal. However, as the fall
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
