PLL PINS
MOTOROLA
DSP56002 PIN DESCRIPTIONS
2 - 13
2.3.4
Debug Request Input (DR)
The debug request input (DR) allows the user to enter the debug mode of operation from
the external command controller. When DR is asserted, it causes the DSP to finish the
current instruction being executed, save the instruction pipeline information, enter the de-
bug mode, and wait for commands to be entered from the DSI line. While in debug mode,
the DR pin lets the user reset the OnCE controller by asserting it and deasserting it after
receiving an acknowledge. It may be necessary to reset the OnCE controller in cases
where synchronization between the OnCE controller and external circuitry is lost. Assert-
ing DR when the DSP is in the WAIT or the STOP state, and keeping it asserted until an
acknowledge pulse in the DSP is produced, sends the DSP into the debug mode. After
receiving the acknowledge, DR must be deasserted before sending the first OnCE com-
mand. For more information, see
Section 10.6 METHODS OF ENTERING THE DEBUG
MODE
in the
DSP56000 Family Manual
(DSP56KFAMUM/AD).
2.4
PLL PINS
The following pins are dedicated to the PLL operation:
•
Analog PLL Circuit Power (PVCC) — The Vcc input is dedicated to the analog
PLL circuits. The voltage should be well regulated and the pin should be pro-
vided with an extremely low impedance path to the Vcc power rail. PVcc should
be bypassed to PGND by a 0.1
µ
F capacitor located as close as possible to the
chip package.
•
Analog PLL Circuit Ground (PGND) — This GND input is dedicated to the an-
alog PLL circuits. The pin should be provided with an extremely low impedance
path to ground. PVcc should be bypassed to PGND by a 0.1
µ
F capacitor locat-
ed as close as possible to the chip package.
•
CKOUT Power (CLVCC) — This input acts as VCC for the CKOUT output. The
voltage should be well regulated and the pin should be provided with an ex-
tremely low impedance path to the VCC power rail. CLVCC should be by-
passed to CLGND by a 0.1
µ
F capacitor located as close as possible to the chip
package.
•
CKOUT Ground (CLGND) — This input acts as GND for the CKOUT output.
The pin should be provided with an extremely low impedance path to ground.
CLVCC should be bypassed to CLGND by a 0.1
µ
F capacitor located as close
as possible to the chip package.
•
PLL Filter Capacitor (PCAP) — This input is used to connect an external ca-
pacitor needed for the PLL filter. One terminal of the capacitor is connected to
PCAP while the other terminal is connected to PVCC. The capacitor value is
specified in the DSP56002 Technical Data Sheet (DSP56002/D).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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