DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR
MOTOROLA
MEMORY MODULES AND OPERATING MODES
3 - 13
3.6
DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR
Section 9 of the
DSP56000 Family Manual
discusses the details of the PLL. The multipli-
cation factor determines the frequency at which the Voltage Controlled Oscillator (VCO)
will oscillate. The user sets the multiplication factor by writing to the MF0-MF11 bits in the
PLL control register.
The DSP56002 PLL multiplication factor is set to 1 during hardware reset, which means
that the Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set
to $000.
SSI IPL
SCI IPL
TIMER IPL
RESERVED
IAL1
IAL0
IAL2
IBL0
IBL1
IBL2
HPL0
HPL1
0
11
10
9
8
7
6
5
4
3
2
1
IRQA MODE
IRQB MODE
RESERVED
HOST IPL
Reserved, read as zero and should be written with zero for future compatibility.
SSL1 SSL0
SCL0
SCL1
12
23
22
21
20
19
18
17
16
15
14
13
Figure 3-4 DSP56002 Interrupt Priority Register (IPR)
TIL1
TIL0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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